Re: Re: [microblaze-uclinux] ml310 development board sram failure

[Paul Hartke <phartke@xxxxxxxxxxxx>]

Try removing all the other additions except:
INST "ddr_dcm/ddr_dcm/DCM_INST"      CLKOUT_PHASE_SHIFT = "FIXED";
INST "ddr_dcm/ddr_dcm/DCM_INST"      PHASE_SHIFT = "72";

Paul

Quoting elynum@xxxxxxx:
> Paul, I've tried to update my MHS with the updated UCF, of course I had
> to go and add and edit the netlist after getting all of that done I got a
> timing constraint error.
>
> The error I got is included in the xflow.log file I've included.
>
> If you don't have a clue on what the error is that I'm getting
>
> I was wondering if you could send me your BSB and MHS and UCF files so I
> test the SRAM.
>
> Thanks,
> >
> > From: Paul Hartke <phartke@xxxxxxxxxxxx>
> > Date: 2006/01/11 Wed PM 12:26:51 EST
> > To: elynum@xxxxxxx
> > CC: microblaze-uclinux@xxxxxxxxxxxxxx,  phartke@xxxxxxxxxxxx
> > Subject: Re: Re: [microblaze-uclinux] ml310 development board sram
> failure
> >
> > You need the phase shift in there:
> > http://www.xilinx.com/products/boards/ml310/current/index.html
> >
>
http://www.xilinx.com/products/boards/ml310/current/reference_designs/base/ml310_base_ucf_update.zip
> >
> > Looks like xilinx has not updated the BSB files to automatically
> include it.
> >
> > Paul
> >
> > Quoting elynum@xxxxxxx:
> > > Yes, I updated to the service pack 2 package and stripped out
> everything
> > > except for the uart and the ddr controller and the sram memory test
> just
> > > hangs.  Here's a copy of my mhs, mss and ucf files.
> > > >
> > > > From: Paul Hartke <phartke@xxxxxxxxxxxx>
> > > > Date: 2006/01/11 Wed AM 11:27:19 EST
> > > > To: microblaze-uclinux@xxxxxxxxxxxxxx,  elynum@xxxxxxx
> > > > CC: microblaze-uclinux@xxxxxxxxxxxxxx
> > > > Subject: Re: [microblaze-uclinux] ml310 development board sram
> failure
> > > >
> > > > I've successfully used Base System Builder created designs with the
> DDR
> > > on
> > > > ml310.  I presume you are using the latest EDK/ISE Service Packs?
> > > >
> > > > Paul
> > > >
> > > > Quoting elynum@xxxxxxx:
> > > > > Hello, does anyone have the ml310 development board from xilinx?
> > > Well,
> > > > > I'm having a problem with the ddr sdram.  I had this same problem
> > > with
> > > > > another development board from avnet.  The memory test for the
> DDR
> > > SDRAM
> > > > > fails.  Now avnet offered the solution in their file that dummy
> > > signals
> > > > > had to be created because the fpga was taking a voltage down.
> That
> > > > > solved that issue but for this ml310 board I'm having the same
> > > problem is
> > > > > that the SDRAM is failing the memory test but the dummy signal
> > > solution I
> > > > > don't think works for this board because it has been laid out
> > > > > differently.  Has someone encountered this problem with the ML310
> dev
> > > > > system.
> > > > >
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