Re: Re: [microblaze-uclinux] ml310 development board sram failure

["Taeweon Suh" <suhtw@xxxxxxxxxxxxxx>]

Hi,

I just want to share my experience with ML310 with EDK 6.3.
I used to use ML310 about a year ago. At that time, I had the same
problem. DDR SDRAM test failure!!.
After patching the DDR-related fix in ucf, it seemed working fine.
(I think you have the same fix in your ucf from the your attached ucf)
But, after building and downloading uclinux, it hung at some point while
booting. I tried to figure out where in uclinux and modified uclunux with
printk statements. But almost every time, the points it hung were
different.
Actually, I got another ML310 from Xilinx after reporting this problem and
the new one showed the same problem.
Afterwards, I switched to Avent board, which worked fine with uclinux.
But, here I didn't use DDR in Avent Virtex-II Pro development (I think,
it's correct) board. Somehow, Avent refused to give me the DDR IP (BSB
didn't have an option to choose DDR in Avent). So, I used SDRAM in the
board. It worked fine.

Taeweon


> Paul, I've tried to update my MHS with the updated UCF, of course I had to
> go and add and edit the netlist after getting all of that done I got a
> timing constraint error.
>
> The error I got is included in the xflow.log file I've included.
>
> If you don't have a clue on what the error is that I'm getting
>
> I was wondering if you could send me your BSB and MHS and UCF files so I
> test the SRAM.
>
> Thanks,
>>
>> From: Paul Hartke <phartke@xxxxxxxxxxxx>
>> Date: 2006/01/11 Wed PM 12:26:51 EST
>> To: elynum@xxxxxxx
>> CC: microblaze-uclinux@xxxxxxxxxxxxxx,  phartke@xxxxxxxxxxxx
>> Subject: Re: Re: [microblaze-uclinux] ml310 development board sram
>> failure
>>
>> You need the phase shift in there:
>> http://www.xilinx.com/products/boards/ml310/current/index.html
>> http://www.xilinx.com/products/boards/ml310/current/reference_designs/base/ml310_base_ucf_update.zip
>>
>> Looks like xilinx has not updated the BSB files to automatically include
>> it.
>>
>> Paul
>>
>> Quoting elynum@xxxxxxx:
>> > Yes, I updated to the service pack 2 package and stripped out
>> everything
>> > except for the uart and the ddr controller and the sram memory test
>> just
>> > hangs.  Here's a copy of my mhs, mss and ucf files.
>> > >
>> > > From: Paul Hartke <phartke@xxxxxxxxxxxx>
>> > > Date: 2006/01/11 Wed AM 11:27:19 EST
>> > > To: microblaze-uclinux@xxxxxxxxxxxxxx,  elynum@xxxxxxx
>> > > CC: microblaze-uclinux@xxxxxxxxxxxxxx
>> > > Subject: Re: [microblaze-uclinux] ml310 development board sram
>> failure
>> > >
>> > > I've successfully used Base System Builder created designs with the
>> DDR
>> > on
>> > > ml310.  I presume you are using the latest EDK/ISE Service Packs?
>> > >
>> > > Paul
>> > >
>> > > Quoting elynum@xxxxxxx:
>> > > > Hello, does anyone have the ml310 development board from xilinx?
>> > Well,
>> > > > I'm having a problem with the ddr sdram.  I had this same problem
>> > with
>> > > > another development board from avnet.  The memory test for the DDR
>> > SDRAM
>> > > > fails.  Now avnet offered the solution in their file that dummy
>> > signals
>> > > > had to be created because the fpga was taking a voltage down.
>> That
>> > > > solved that issue but for this ml310 board I'm having the same
>> > problem is
>> > > > that the SDRAM is failing the memory test but the dummy signal
>> > solution I
>> > > > don't think works for this board because it has been laid out
>> > > > differently.  Has someone encountered this problem with the ML310
>> dev
>> > > > system.
>> > > >
>> > >
>> >
>>
>>
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>> Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
>> Mailing List Archive :
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>>
>>
>


----------------------------------------------
Taeweon Suh

Ph.D. Candidate
School of Electrical and Computer Engineering
Georgia Institute of Technology
Atlanta, Georgia USA

Lab: CoC345
Tel: +1-404-385-6273
E-mail: suhtw@xxxxxxxxxxxxxx
----------------------------------------------

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