Using Xilinx's bit file, I was able to see the memory test on my ml310 board come up fine. Now when I use their mb_ph shift files. It looks like they left things out so it fails. Now in trying to build my own system incorporating the changes for the phase shift I get the hyperterminal console to come up and say "Incrementing through all the phases and reporting the passing ranges" but then it hangs after that. I copied their .c file over and changed some parameters because they didn't use the uart lite but I'm having a hard time finding out why it stops at that point. I've encluded my .c files and mhs. Thanks for any help.
Attachment:
system.mhs
Description: Binary data
PARAMETER VERSION = 2.2.0 BEGIN OS PARAMETER OS_NAME = standalone PARAMETER OS_VER = 1.00.a PARAMETER PROC_INSTANCE = microblaze_0 PARAMETER STDIN = RS232_Uart PARAMETER STDOUT = RS232_Uart END BEGIN PROCESSOR PARAMETER DRIVER_NAME = cpu PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = microblaze_0 PARAMETER COMPILER = mb-gcc PARAMETER ARCHIVER = mb-ar PARAMETER XMDSTUB_PERIPHERAL = debug_module END BEGIN DRIVER PARAMETER DRIVER_NAME = opbarb PARAMETER DRIVER_VER = 1.02.a PARAMETER HW_INSTANCE = mb_opb END BEGIN DRIVER PARAMETER DRIVER_NAME = uartlite PARAMETER DRIVER_VER = 1.00.b PARAMETER HW_INSTANCE = debug_module END BEGIN DRIVER PARAMETER DRIVER_NAME = bram PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = dlmb_cntlr END BEGIN DRIVER PARAMETER DRIVER_NAME = bram PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = ilmb_cntlr END BEGIN DRIVER PARAMETER DRIVER_NAME = uartlite PARAMETER DRIVER_VER = 1.00.b PARAMETER HW_INSTANCE = RS232_Uart END BEGIN DRIVER PARAMETER DRIVER_NAME = ddr PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = DDR_SDRAM_32Mx64 END BEGIN DRIVER PARAMETER DRIVER_NAME = tmrctr PARAMETER DRIVER_VER = 1.00.b PARAMETER HW_INSTANCE = opb_timer_1 END BEGIN DRIVER PARAMETER DRIVER_NAME = intc PARAMETER DRIVER_VER = 1.00.c PARAMETER HW_INSTANCE = opb_intc_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = generic PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = ORGate_1 END BEGIN DRIVER PARAMETER DRIVER_NAME = gpio PARAMETER DRIVER_VER = 2.00.a PARAMETER HW_INSTANCE = opb_gpio_0 END
Attachment:
system.bsb
Description: Binary data
/*******************************************************************/
/* */
/* This file is automatically generated by linker script generator.*/
/* */
/* Version: Xilinx EDK 7.1.2EDK_H.12.5.1 */
/* */
/* Copyright (c) 2004 Xilinx, Inc. All rights reserved. */
/* */
/* Description : MicroBlaze Linker Script */
/* */
/*******************************************************************/
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x400;
/* Define Memories in the system */
MEMORY
{
DDR_SDRAM_32Mx64_C_MEM0_BASEADDR : ORIGIN = 0x30000000, LENGTH = 0x0FFFFFFF
ilmb_cntlr_dlmb_cntlr : ORIGIN = 0x00000000, LENGTH = 0x00003FFF
}
/* Specify the default entry point to the program */
ENTRY(_start)
/* Define the sections, and where they are mapped in memory */
SECTIONS
{
.text : {
__text_start = .;
*(.text)
*(.text.*)
*(.gnu.linkonce.t*)
__text_end = .;
} > DDR_SDRAM_32Mx64_C_MEM0_BASEADDR
.rodata : {
__rodata_start = .;
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r*)
__rodata_end = .;
} > DDR_SDRAM_32Mx64_C_MEM0_BASEADDR
.sdata2 : {
. = ALIGN(8);
__sdata2_start = .;
*(.sdata2)
. = ALIGN(8);
__sdata2_end = .;
} > DDR_SDRAM_32Mx64_C_MEM0_BASEADDR
.sbss2 : {
__sbss2_start = .;
*(.sbss2)
__sbss2_end = .;
} > DDR_SDRAM_32Mx64_C_MEM0_BASEADDR
.data : {
. = ALIGN(4);
__data_start = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
__data_end = .;
} > DDR_SDRAM_32Mx64_C_MEM0_BASEADDR
.sdata : {
. = ALIGN(8);
__sdata_start = .;
*(.sdata)
__sdata_end = .;
} > DDR_SDRAM_32Mx64_C_MEM0_BASEADDR
.sbss : {
. = ALIGN(4);
__sbss_start = .;
*(.sbss)
. = ALIGN(8);
__sbss_end = .;
} > DDR_SDRAM_32Mx64_C_MEM0_BASEADDR
.bss : {
. = ALIGN(4);
__bss_start = .;
*(.bss)
*(COMMON)
. = ALIGN(4);
__bss_end = .;
} > DDR_SDRAM_32Mx64_C_MEM0_BASEADDR
.eh_frame : {
__eh_frame_start = .;
*(.eh_frame)
__eh_frame_end = .;
} > DDR_SDRAM_32Mx64_C_MEM0_BASEADDR
PROVIDE (_SDA_BASE_ = __sdata_start + (__sbss_end - __sdata_start / 2 ));
PROVIDE (_SDA2_BASE_ = __sdata2_start + (__sbss2_end - __sdata2_start / 2 ));
/* Generate Stack and Heap definitions */
bss_stack : {
. = ALIGN(8);
_heap = .;
_heap_start = _heap;
. += _HEAP_SIZE;
. += _STACK_SIZE;
. = ALIGN(8);
_stack = .;
__stack = _stack;
} > DDR_SDRAM_32Mx64_C_MEM0_BASEADDR
}
Attachment:
system.ucf
Description: Binary data
/*
* * Copyright (c) 2004 Xilinx, Inc. All rights reserved.
*
* Xilinx, Inc.
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE.
*/
/*
* Xilinx EDK 6.3 EDK_Gmm.12.3
*
* This file is a sample test application
*
* This application is intended to test and/or illustrate some
* functionality of your system. The contents of this file may
* vary depending on the IP in your system and may use existing
* IP driver functions. These drivers will be generated in your
* XPS project when you run the "Generate Libraries" menu item
* in XPS.
*
* Your XPS project directory is at:
* H:\applications\systems\mb_ph_shift
*/
// Located in: microblaze_0/include/xparameters.h
#include "xparameters.h"
//#include "xuartns550_l.h"
#include "xgpio_l.h"
#include "xstatus.h"
#include "stdio.h"
#include "xutil.h"
#define MEM_TEST_LENGTH 0x4000 /* 16 KBytes */
/************************** Constant Definitions ****************************/
#define UART_BASEADDR XPAR_RS232_UART_BASEADDR
#define UART_CLOCK XPAR_XUARTNS550_CLOCK_HZ
#define UART_BAUDRATE 9600 /* real hardware */
#define GPIO_0_BASEADDR XPAR_OPB_GPIO_0_BASEADDR
static int MemoryTest(Xuint32 *Baseaddr, Xuint32 ByteLength);
/************************** Function Prototypes *****************************/
extern XStatus XPlbDdrSdram_Test(void);
extern char inbyte ();
XStatus XPlbDdrSdram_Test(void)
{
Xuint32 *BaseAddr;
Xuint32 ByteLength;
/*
* Initialize base address and length of the memory to test.
*/
BaseAddr = (Xuint32*)(XPAR_DDR_SDRAM_32MX64_MEM0_BASEADDR);
ByteLength = XPAR_DDR_SDRAM_32MX64_MEM0_HIGHADDR - (Xuint32)BaseAddr + 1;
if (ByteLength > MEM_TEST_LENGTH)
{
ByteLength = MEM_TEST_LENGTH;
}
/*
* Test the memory
*/
if (MemoryTest(BaseAddr, ByteLength) == 0)
{
return XST_SUCCESS;
}
else
{
return XST_FAILURE;
}
}
/****************************************************************************/
/**
*
* Test a memory block in destructive way. all 32/16/8-bit wide tests are
* executed.
*
*
* @param BaseAddr is the starting address of the memory block to test.
*
* @param ByteLength is the size, in bytes, of the memory block.
*
* @return The number of memory test errors.
*
* @note None.
*
****************************************************************************/
static int MemoryTest(Xuint32 *BaseAddr, Xuint32 ByteLength)
{
XStatus Value;
/*
* 32-bit wide memory test
*/
Value = XUtil_MemoryTest32(BaseAddr, ByteLength/sizeof(Xuint32), 0,
XUT_ALLMEMTESTS);
if (Value != XST_SUCCESS)
{
return 1;
}
/*
* 16-bit wide memory test
*/
Value = XUtil_MemoryTest16((Xuint16*)BaseAddr,
ByteLength/sizeof(Xuint16), 0, XUT_ALLMEMTESTS);
if (Value != XST_SUCCESS)
{
return 1;
}
/*
* 8-bit wide memory test
*/
Value = XUtil_MemoryTest8((Xuint8*)BaseAddr, ByteLength/sizeof(Xuint8),
0, XUT_ALLMEMTESTS);
if (Value != XST_SUCCESS)
{
return 1;
}
return 0;
}
//====================================================
int main (void) {
Xuint32 i, j;
Xuint32 passed_memtest = 0;
Xuint32 passing_value = 0;
/* setup 16550 Uart */
// XUartNs550_SetBaud(UART_BASEADDR, UART_CLOCK, UART_BAUDRATE);
// XUartNs550_mSetLineControlReg(UART_BASEADDR, XUN_LCR_8_DATA_BITS);
/* set led bits to all output */
XGpio_mSetDataDirection(GPIO_0_BASEADDR, 1, 0xFFFFFFFE);
/* print test title */
xil_printf("\r\nDCM PHASE SHIFT TEST\r\n");
xil_printf("____________________\r\n");
xil_printf("\r\n\r\nMoving the initial phase to -255");
/* moving the initial phase from 0 to -255 */
for (i = 0; i <= 254; i++)
{
if ((i%80) == 0)
{
xil_printf("\r\n");
}
/* decrease phase shift of the DCM by 1 */
for (j = 0; j < 500000; j++);
XGpio_mSetDataReg(GPIO_0_BASEADDR, 1, 2);
for (j = 0; j < 500000; j++);
XGpio_mSetDataReg(GPIO_0_BASEADDR, 1, 0);
xil_printf(".");
}
xil_printf(" Done\r\n");
xil_printf("\r\nIncrementing through all the phases and reporting the passing ranges\r\n\r\n");
/* this loop moves the phase from -255 to 255 and performs a memory test at each phase */
for (i = 0; i <= 511; i++)
{
xil_printf("\r\n TESTING\r\n");
/* if the memory test on DDR passed */
if (XPlbDdrSdram_Test() == XST_SUCCESS)
{
xil_printf("\r\n TESTING 1\r\n");
/* if this is the first time the test passes after a failure, record the phase value */
if (passed_memtest == 0)
{
xil_printf("\r\n TESTING 4\r\n");
passed_memtest = 1;
passing_value = i;
}
}
/* if the memory test on DDR did not pass */
else if (XPlbDdrSdram_Test() == XST_FAILURE)
{
/* if this is the first time the test fails after a success, report the passing range */
if (passed_memtest == 1)
{
passed_memtest = 0;
xil_printf ("Passing range is %d to %d, optimal phase shift for this range is %d\r\n",
(passing_value - 255), (i - 255 - 1), ((i - 1 - passing_value)/2 + passing_value - 255));
if (((i - 1 - passing_value)/2 + passing_value) > 255)
{
xil_printf ("\r\nSet your DDR feedback clock phase shift to %d\r\n",
((i - 1 - passing_value)/2 + passing_value - 255));
}
}
}
else
{
}
/* increase phase shift of the DCM by 1 */
for (j = 0; j < 500000; j++);
XGpio_mSetDataReg(GPIO_0_BASEADDR, 1, 3);
for (j = 0; j < 500000; j++);
XGpio_mSetDataReg(GPIO_0_BASEADDR, 1, 1);
}
xil_printf("\r\nFinished testing\r\n");
return 0;
}
/*
* * Copyright (c) 2004 Xilinx, Inc. All rights reserved.
*
* Xilinx, Inc.
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE.
*/
/*
* Xilinx EDK 7.1.2 EDK_H.12.5.1
*
* This file is a sample test application
*
* This application is intended to test and/or illustrate some
* functionality of your system. The contents of this file may
* vary depending on the IP in your system and may use existing
* IP driver functions. These drivers will be generated in your
* XPS project when you run the "Generate Libraries" menu item
* in XPS.
*
* Your XPS project directory is at:
* C:\ml310_dev
*/
// Located in: microblaze_0/include/xparameters.h
#include "xparameters.h"
#include "xutil.h"
//====================================================
int main (void) {
/*
* Enable and initialize cache
*/
microblaze_init_icache_range(0, 2048);
microblaze_enable_icache();
microblaze_init_dcache_range(0, 8192);
microblaze_enable_dcache();
print("-- Entering main() --\r\n");
/*
* MemoryTest routine will not be run for the memory at
* 0x00000000 (dlmb_cntlr)
* because it is being used to hold a part of this application program
*/
/* Testing DDR Memory (DDR_SDRAM_32Mx64)*/
{
XStatus status;
print("Starting MemoryTest for DDR_SDRAM_32Mx64:\r\n");
print(" Running 32-bit test...");
status = XUtil_MemoryTest32((Xuint32*)XPAR_DDR_SDRAM_32MX64_MEM0_BASEADDR, 1024, 0xAAAA5555, XUT_ALLMEMTESTS);
if (status == XST_SUCCESS) {
print("PASSED!\r\n");
}
else {
print("FAILED!\r\n");
}
print(" Running 16-bit test...");
status = XUtil_MemoryTest16((Xuint16*)XPAR_DDR_SDRAM_32MX64_MEM0_BASEADDR, 2048, 0xAA55, XUT_ALLMEMTESTS);
if (status == XST_SUCCESS) {
print("PASSED!\r\n");
}
else {
print("FAILED!\r\n");
}
print(" Running 8-bit test...");
status = XUtil_MemoryTest8((Xuint8*)XPAR_DDR_SDRAM_32MX64_MEM0_BASEADDR, 4096, 0xA5, XUT_ALLMEMTESTS);
if (status == XST_SUCCESS) {
print("PASSED!\r\n");
}
else {
print("FAILED!\r\n");
}
}
/*
* Disable cache and reinitialize it so that other
* applications can be run with no problems
*/
microblaze_disable_dcache();
microblaze_init_dcache_range(0, 8192);
microblaze_disable_icache();
microblaze_init_icache_range(0, 2048);
print("-- Exiting main() --\r\n");
return 0;
}
/*
* * Copyright (c) 2004 Xilinx, Inc. All rights reserved.
*
* Xilinx, Inc.
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE.
*/
/*
* Xilinx EDK 7.1.2 EDK_H.12.5.1
*
* This file is a sample test application
*
* This application is intended to test and/or illustrate some
* functionality of your system. The contents of this file may
* vary depending on the IP in your system and may use existing
* IP driver functions. These drivers will be generated in your
* XPS project when you run the "Generate Libraries" menu item
* in XPS.
*
* Your XPS project directory is at:
* C:\ml310_dev
*/
// Located in: microblaze_0/include/xparameters.h
#include "xparameters.h"
//====================================================
int main (void) {
/*
* Enable and initialize cache
*/
microblaze_init_icache_range(0, 2048);
microblaze_enable_icache();
microblaze_init_dcache_range(0, 8192);
microblaze_enable_dcache();
print("-- Entering main() --\r\n");
{
int retval;
print("\r\nRunning UartLiteSelfTestExample() for debug_module...\r\n");
retval = UartLiteSelfTestExample(XPAR_DEBUG_MODULE_DEVICE_ID);
if (retval == 0) {
print("UartLiteSelfTestExample PASSED\r\n");
}
else {
print("UartLiteSelfTestExample FAILED\r\n");
}
}
/*
* Peripheral SelfTest will not be run for RS232_Uart
* because it has been selected as the STDOUT device
*/
/*
* Disable cache and reinitialize it so that other
* applications can be run with no problems
*/
microblaze_disable_dcache();
microblaze_init_dcache_range(0, 8192);
microblaze_disable_icache();
microblaze_init_icache_range(0, 2048);
print("-- Exiting main() --\r\n");
return 0;
}