[microblaze-uclinux] Problem with XAPP806: Determining DCM Phase Shift for ML310 board

["Nob Kladjarern" <nob.gatech@xxxxxxxxx>]

Hello,

 

I have read on here that people having problem with the DDR timing on the ML310 board should try to follow the  Xilinx application note XAPP806. I have tried to follow this note, but I ran into something unexpected. Can someone who has experience with this help point out what I might possibly have done wrong please?

 

Basically, I have followed the note and I was able to run the application. However, I get the result that the memory test passed for all phase shift. So I was not able to determine the optimal phase shift. As I understand it, it is not possible that the memory test will pass for all the DCM phase shift. Has anyone experience it passing for all range like this? Any idea what I might have done wrong here?

 

Or should I just be thankful that it passed and just fix the phase shift to 0?

 

Thank you for any help.

 

Sincerely,

 

Nob Kladjarern