Re: [microblaze-uclinux] System hangs with I-cache enabled

[John Williams <jwilliams@xxxxxxxxxxxxxx>]

Hi Alex,

Alex Krasnov wrote:

>> There was a bug in the mch_opb_ddr core, in EDK7.1, and I am not sure if
>> it has been completely resolved.  It caused pipeline stalls like that
>> you describe.
> 
> What is the nature of this bug? Is there a work-around?

Xilinx use a common low-level DDR core, around which the various plb, opb and
mch_opb wrappers live.  The bug was actually caused in the low level DDR core,
that caused an MCH cacheline request (4 words) to stall, thus causing a pipeline
stall in the microblaze.

At that time, the work-around was to not use the core.

But, I've never seen problems like this in the opb_ddr core - only the mch_opb_ddr

>> Also, there was a bug in the MicroBlaze v4.00.a core, around the same
>> time, whereby partial cache invalidate operations would cause problems
>> when the MCH (CacheLink) channels were used.
> 
> What is the nature of this bug? Does it occur when invalidating only
> part of a cache line? Also, from what I understand, microblaze_v4_00_a
> is the latest version, so is this bug still active?

The bug, if I remember rightly, was that a cache flush on anything other than
the entire cache (not just cache line), would cause problems.  Thus the work
around that's visible in linux/include/asm-microblaze/pgalloc.h

As for the version number, Xilinx increments core revision numbers based on
features, *not* bug fixes.  So, the core version number alone is not sufficient
to determine whether a bug is fixed or not, it also depends on which tool
release and service pack.

I have not had a chance to test the v4.00.a from EDK8.1 with most recent service
pack, against this bug, so can't say for sure whether it is still an issue.

Goran, or Vasanth, if you are listening, can you shed any light on this one?

John


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