RE: [microblaze-uclinux] Multiple Microblaze cores

Hi Wei,

First of - kudos to you and your project team for pressing on inspite of many hurdles! It is an interesting project that has been well executed.

With regards to your difficulties with IP cores and MicroBlaze systems-- we (Xilinx) are aware of at least some of the issues and are interested in the others. Indeed, some of them may have already been fixed in the latest releases. I will reach you via a separate mail to get into specifics.

Please do not hesitate to get in touch with us in the future regarding any questions or issues that you face. We may be able to offer help earlier in the iteration.

thanks,

Vasanth Asokan

Software Engineer

Embedded Processor Division

Xilinx Inc.

From: owner-microblaze-uclinux@xxxxxxxxxxxxxx [mailto:owner-microblaze-uclinux@xxxxxxxxxxxxxx] On Behalf Of Wei Xu
Sent: Friday, May 19, 2006 12:05 PM
To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: Re: [microblaze-uclinux] Multiple Microblaze cores

Hi,

We have put 4-6 Microblaze into the FPGA on XUP board w/ 256MB RAM, each running uClinux with many apps. It was not easy, due to many bugs in the existing Xilinx IP cores when you put multiple microblazes in, and we end up reimplementing several IP cores, including the memory controller.

We have a report online at http://www.cs.berkeley.edu/~xuw/ramp.pdf

Note that this report is not polished to publishable quality, please view it as a extended summary. Please contact us if you have further questions. I am glad someone else is considering the same thing. I believe we will have a lot experiences to share.

Thanks,

Wei

On 5/19/06, Kapelonis Kostis <kkapelon@xxxxxxxxxxxx> wrote:

Hello

>From the contents of this list it seems to me
that 99% of people use uclinux on a single Microblaze
cpu.

Now I guess that some of you have already some
designs with 2 Microblaze cpus but with each
one running a separate OS (2 uclinux kernels).

I am thinking of adding 4 Microblaze cores to
an FPGA and run _one_ uclinux kernel on them.
It won't be strictly SMP-ish but you get the idea.

But before I deal with the software, what about the hardware?
Can 4 Microblaze core share resources on an FPGA in a deterministic way?

I know that my XUP board has enough space for 4 Microblaze cores.
I don't know what happens if all four of them attempt to access
the OPB DDR memory chip or any other hardware resource at the same time.
Will it work?

Have you any experience with this?
Have you observed any scalability issues with more than 2 Microblaze
CPUs?

Kostis

___________________________
microblaze-uclinux mailing list
microblaze-uclinux@xxxxxxxxxxxxxx
Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/