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Hi all, Has anyone had problems with the EMAC driver under uClinux? We
are trying to bring up a board with uClinux and John William’s toolchain.
We have a Spartan 3 with one Microblaze core and one EMAC 10/100 core. We know
that the hardware works on this board – the same board was up and running
several months ago with a uClinux image including the EMAC core. We are attempting to duplicate our past successes but the
network interface is not working. Transmits never get sent out over the MII
interface, even though XEmac_SgSend() returns XST_SUCCESS. Incoming packets are
received through the MII but XEmac_IntrHandlerDma() detects an EMAC related
error, which upon further digging in HandleEmacDmaIntr() yields a status of 0xc01a.
In a nutshell, this value states that the receive FIFO has overflowed, a frame
has been missed, a receive error has occurred, receive is complete, and the
transmit FIFO is empty. We have not modified the uClinux-Xilinx driver code at
all (other than printk() statements to debug this problem). Any suggestions? I have included the MHS file below, which
was built using the Xilinx Platform Studio 7.1. Steve # ############################################################################## # Created by Base System Builder Wizard for Xilinx EDK 6.3 # Thu Feb 19 14:26:41 2005 # Target Board: Precision Energy Services - DAM # Family:
spartan3 # Device:
xc3s1500 # Package: fg456 # Speed Grade: -4 # ############################################################################## PARAMETER VERSION = 2.1.0 PORT LED_GPIO_IO = LED_GPIO_IO, VEC = [0:5], DIR =
INOUT PORT console_uart_TX = console_uart_TX, DIR = OUT PORT console_uart_RX = console_uart_RX, DIR = IN PORT memcon_A = memcon_A, VEC = [9:30], DIR = OUT PORT memcon_DQ = memcon_DQ, VEC = [0:15], DIR = INOUT PORT memcon_BEN = memcon_BEN, VEC = [0:1], DIR = OUT PORT memcon_CEN = memcon_CEN, VEC = [0:5], DIR = OUT PORT memcon_OEN = memcon_OEN, VEC = [0:5], DIR = OUT PORT memcon_WEN = memcon_WEN, DIR = OUT PORT io_sel = iosys_bank_sel, VEC = [0:2], DIR = OUT PORT io_gab = iosys_gab, DIR = OUT PORT io_gba = iosys_gba, DIR = OUT PORT io_cpab = iosys_cpab, DIR = OUT PORT io_cpba = iosys_cpba, DIR = OUT PORT io_sab = iosys_sab, DIR = OUT PORT io_sba = iosys_sba, DIR = OUT PORT io_en_bank0 = io_en_bank0, VEC
= [0:1], DIR = INOUT PORT sys_rst = sys_rst_s, DIR = IN PORT sys_clk = sys_clk_ext, DIR = IN, SIGIS = CLK PORT iosys_DIO = io_data, VEC = [15:0], DIR = INOUT PORT opb_ethernet_0_PHY_Mii_clk =
opb_ethernet_0_PHY_Mii_clk, DIR = INOUT PORT opb_ethernet_0_PHY_tx_en =
opb_ethernet_0_PHY_tx_en, DIR = OUT PORT opb_ethernet_0_PHY_tx_data =
opb_ethernet_0_PHY_tx_data, VEC = [3:0], DIR = OUT PORT opb_ethernet_0_PHY_Mii_data =
opb_ethernet_0_PHY_Mii_data, DIR = INOUT PORT opb_ethernet_0_PHY_tx_clk =
opb_ethernet_0_PHY_tx_clk, DIR = IN PORT opb_ethernet_0_PHY_rx_clk =
opb_ethernet_0_PHY_rx_clk, DIR = IN PORT opb_ethernet_0_PHY_crs = opb_ethernet_0_PHY_crs,
DIR = IN PORT opb_ethernet_0_PHY_dv = opb_ethernet_0_PHY_dv,
DIR = IN PORT opb_ethernet_0_PHY_rx_data =
opb_ethernet_0_PHY_rx_data, VEC = [3:0], DIR = IN PORT opb_ethernet_0_PHY_col = opb_ethernet_0_PHY_col,
DIR = IN PORT opb_ethernet_0_PHY_rx_er = opb_ethernet_0_PHY_rx_er,
DIR = IN PORT opb_ethernet_0_PHY_rst_n =
opb_ethernet_0_PHY_rst_n, DIR = OUT PORT DUMMY_OUT = phy_p0ac, DIR = OUT PORT PHY_P0AC = phy_p0ac, DIR = IN BEGIN dcm_module PARAMETER INSTANCE = dcm_system PARAMETER HW_VER = 1.00.a PARAMETER C_CLK0_BUF = TRUE PARAMETER C_CLKFX_BUF = TRUE PARAMETER C_CLKFX_MULTIPLY = 6 PARAMETER C_CLKFX_DIVIDE = 5 PARAMETER C_CLKIN_PERIOD = 16.666 PARAMETER C_DLL_FREQUENCY_MODE = HIGH PARAMETER C_DFS_FREQUENCY_MODE = LOW PORT CLKFX = sys_clk_s PORT CLKIN = sys_clk_ext PORT CLKFB = dcm_system_CLK0 PORT CLK0 = dcm_system_CLK0 END BEGIN microblaze PARAMETER INSTANCE = microblaze_0 PARAMETER HW_VER = 4.00.a PARAMETER C_USE_DIV = 1 PARAMETER C_USE_BARREL = 1 PARAMETER C_DEBUG_ENABLED = 1 PARAMETER C_NUMBER_OF_PC_BRK = 1 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 2 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 2 PARAMETER C_USE_ICACHE = 0 PARAMETER C_CACHE_BYTE_SIZE = 2048 PARAMETER C_USE_DCACHE = 0 PARAMETER C_ALLOW_ICACHE_WR = 1 PARAMETER C_ALLOW_DCACHE_WR = 1 PARAMETER C_ICACHE_BASEADDR = 0x80000000 PARAMETER C_ICACHE_HIGHADDR = 0x8FFFFFFF PARAMETER C_DCACHE_BASEADDR = 0x80000000 PARAMETER C_DCACHE_HIGHADDR = 0x8FFFFFFF PARAMETER C_DCACHE_BYTE_SIZE = 2048 BUS_INTERFACE DLMB = dlmb BUS_INTERFACE ILMB = ilmb BUS_INTERFACE DOPB = mb_opb BUS_INTERFACE IOPB = mb_opb PORT INTERRUPT = Interrupt PORT CLK = sys_clk_s END BEGIN opb_mdm PARAMETER INSTANCE = mdm PARAMETER HW_VER = 2.00.a PARAMETER C_BASEADDR = 0xFE005000 PARAMETER C_HIGHADDR = 0xFE0050FF PARAMETER C_MB_DBG_PORTS = 1 BUS_INTERFACE SOPB = mb_opb PORT OPB_Clk = sys_clk_s END BEGIN lmb_v10 PARAMETER INSTANCE = ilmb PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 1 PORT LMB_Clk = sys_clk_s PORT SYS_Rst = sys_rst_s END BEGIN lmb_v10 PARAMETER INSTANCE = dlmb PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 1 PORT LMB_Clk = sys_clk_s PORT SYS_Rst = sys_rst_s END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = ilmb_cntlr PARAMETER HW_VER = 1.00.b PARAMETER C_MASK = 0x2000 PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00007fff BUS_INTERFACE SLMB = ilmb BUS_INTERFACE BRAM_PORT = ilmb_port END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = dlmb_cntlr PARAMETER HW_VER = 1.00.b PARAMETER C_MASK = 0x2000 PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00007fff BUS_INTERFACE SLMB = dlmb BUS_INTERFACE BRAM_PORT = dlmb_port END BEGIN bram_block PARAMETER INSTANCE = lmb_bram PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = ilmb_port BUS_INTERFACE PORTB = dlmb_port END BEGIN opb_v20 PARAMETER INSTANCE = mb_opb PARAMETER HW_VER = 1.10.c PARAMETER C_EXT_RESET_HIGH = 1 PORT SYS_Rst = sys_rst_s PORT OPB_Clk = sys_clk_s END BEGIN opb_intc PARAMETER INSTANCE = system_intc PARAMETER HW_VER = 1.00.c PARAMETER C_BASEADDR = 0xFE003000 PARAMETER C_HIGHADDR = 0xFE0030FF BUS_INTERFACE SOPB = mb_opb PORT Irq = Interrupt PORT Intr = console_uart_interrupt &
opb_ethernet_0_IP2INTC_Irpt & system_timer_Interrupt PORT OPB_Clk = sys_clk_s END BEGIN opb_timer PARAMETER INSTANCE = system_timer PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0xFE001000 PARAMETER C_HIGHADDR = 0xFE0010FF PARAMETER C_ONE_TIMER_ONLY = 1 PARAMETER C_COUNT_WIDTH = 32 BUS_INTERFACE SOPB = mb_opb PORT Freeze = net_gnd PORT Interrupt = system_timer_Interrupt PORT OPB_Clk = sys_clk_s END BEGIN opb_emc PARAMETER INSTANCE = system_memcon PARAMETER HW_VER = 1.10.b PARAMETER C_BASEADDR = 0xFE000000 PARAMETER C_HIGHADDR = 0xFE0001FF # PARAMETER C_NUM_BANKS_MEM = 4 # new SRAM PARAMETER C_NUM_BANKS_MEM = 6 PARAMETER C_OPB_CLK_PERIOD_PS = 13889 PARAMETER C_MAX_MEM_WIDTH = 16 PARAMETER C_MEM0_WIDTH = 16 PARAMETER C_MEM1_WIDTH = 16 PARAMETER C_MEM2_WIDTH = 16 PARAMETER C_MEM3_WIDTH = 16 # new SRAM PARAMETER C_MEM4_WIDTH = 16 # new SRAM PARAMETER C_MEM5_WIDTH = 16 PARAMETER C_MEM0_BASEADDR = 0x80000000 PARAMETER C_MEM0_HIGHADDR = 0x801FFFFF PARAMETER C_MEM1_BASEADDR = 0x80200000 PARAMETER C_MEM1_HIGHADDR = 0x803FFFFF PARAMETER C_MEM2_BASEADDR = 0xFF000000 PARAMETER C_MEM2_HIGHADDR = 0xFF7FFFFF PARAMETER C_MEM3_BASEADDR = 0xFF800000 PARAMETER C_MEM3_HIGHADDR = 0xFFFFFFFF # new SRAM PARAMETER C_MEM4_BASEADDR = 0x80400000 # new SRAM PARAMETER C_MEM4_HIGHADDR = 0x805FFFFF # new SRAM PARAMETER C_MEM5_BASEADDR = 0x80600000 # new SRAM PARAMETER C_MEM5_HIGHADDR = 0x807FFFFF PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_1 = 1 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_2 = 0 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_3 = 0 # new SRAM PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_4 = 1 # new SRAM PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_5 = 1 PARAMETER C_SYNCH_MEM_0 = 0 PARAMETER C_SYNCH_MEM_1 = 0 PARAMETER C_SYNCH_MEM_2 = 0 PARAMETER C_SYNCH_MEM_3 = 0 # new SRAM PARAMETER C_SYNCH_MEM_4 = 0 # new SRAM PARAMETER C_SYNCH_MEM_5 = 0 PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_0 = 27000 PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_0 = 27000 PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_0 = 23000 PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_0 = 27000 PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_0 = 27000 PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_0 = 27000 PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_0 = 27000 PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_1 = 27000 PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_1 = 27000 PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_1 = 23000 PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_1 = 27000 PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_1 = 27000 PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_1 = 27000 PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_1 = 27000 PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_2 = 150000 PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_2 = 55000 PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_2 = 70000 PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_2 = 150000 PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_2 = 55000 PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_2 = 15000 PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_2 = 35000 PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_3 = 150000 PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_3 = 55000 PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_3 = 70000 PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_3 = 150000 PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_3 = 55000 PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_3 = 15000 PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_3 = 35000 # new SRAM PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_4 = 27000 # new SRAM PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_4 = 27000 # new SRAM PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_4 = 23000 # new SRAM PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_4 = 27000 # new SRAM PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_4 = 27000 # new SRAM PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_4 = 27000 # new SRAM PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_4 = 27000 # new SRAM PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_5 = 27000 # new SRAM PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_5 = 27000 # new SRAM PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_5 = 23000 # new SRAM PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_5 = 27000 # new SRAM PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_5 = 27000 # new SRAM PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_5 = 27000 # new SRAM PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_5 = 27000 PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 0 BUS_INTERFACE SOPB = mb_opb PORT OPB_Clk = sys_clk_s PORT Mem_WEN = memcon_WEN PORT Mem_OEN = memcon_OEN PORT Mem_DQ = memcon_DQ PORT Mem_BEN = memcon_BEN PORT Mem_CEN = memcon_CEN PORT Mem_A = memcon_A_split END BEGIN util_bus_split PARAMETER INSTANCE = system_memcon_addr_split PARAMETER HW_VER = 1.00.a PARAMETER C_SIZE_IN = 32 PARAMETER C_LEFT_POS = 9 PARAMETER C_SPLIT = 31 PORT Out1 = memcon_A PORT Sig = memcon_A_split END BEGIN opb_gpio PARAMETER INSTANCE = system_gpio PARAMETER HW_VER = 3.01.b PARAMETER C_GPIO_WIDTH = 6 PARAMETER C_ALL_INPUTS = 0 PARAMETER C_BASEADDR = 0xFE004000 PARAMETER C_HIGHADDR = 0xFE0041FF BUS_INTERFACE SOPB = mb_opb PORT OPB_Clk = sys_clk_s PORT GPIO_IO = LED_GPIO_IO END BEGIN opb_gpio PARAMETER INSTANCE = io_ctl_en_bank0 PARAMETER HW_VER = 3.01.b PARAMETER C_BASEADDR = 0xFE007000 PARAMETER C_HIGHADDR = 0xFE0071FF PARAMETER C_GPIO_WIDTH = 2 PARAMETER C_ALL_INPUTS = 0 BUS_INTERFACE SOPB = mb_opb PORT OPB_Clk = sys_clk_s PORT GPIO_IO = io_en_bank0 END BEGIN opb_uartlite PARAMETER INSTANCE = console_uart PARAMETER HW_VER = 1.00.b PARAMETER C_BASEADDR = 0xFE002000 PARAMETER C_HIGHADDR = 0xFE0020FF PARAMETER C_DATA_BITS = 8 PARAMETER C_CLK_FREQ = 72000000 PARAMETER C_BAUDRATE = 115200 PARAMETER C_USE_PARITY = 0 BUS_INTERFACE SOPB = mb_opb PORT OPB_Clk = sys_clk_s PORT Interrupt = console_uart_Interrupt PORT RX = console_uart_RX END BEGIN dam_io PARAMETER INSTANCE = iosys PARAMETER HW_VER = 1.00.a PARAMETER C_BASEADDR = 0xFE006000 PARAMETER C_HIGHADDR = 0xfe0060ff BUS_INTERFACE SOPB = mb_opb PORT cpab = iosys_cpab PORT DIO = io_data PORT cpba = iosys_cpba PORT sab = iosys_sab PORT gba = iosys_gba PORT gab = iosys_gab PORT sba = iosys_sba PORT OPB_Clk = sys_clk_s PORT bank_sel = iosys_bank_sel END BEGIN opb_ethernet PARAMETER INSTANCE = opb_ethernet_0 PARAMETER HW_VER = 1.02.a PARAMETER C_BASEADDR = 0xFE008000 PARAMETER C_HIGHADDR = 0xfe00bfff PARAMETER C_IPIF_RDFIFO_DEPTH = 16384 PARAMETER C_IPIF_WRFIFO_DEPTH = 16384 PARAMETER C_OPB_CLK_PERIOD_PS = 13889 PARAMETER C_DMA_PRESENT = 3 BUS_INTERFACE MSOPB = mb_opb PORT PHY_rx_en =
opb_ethernet_0_PHY_rx_en PORT PHY_rx_data =
opb_ethernet_0_PHY_rx_data PORT PHY_rx_clk = opb_ethernet_0_PHY_rx_clk PORT OPB_Clk = sys_clk_s PORT emac_intrpts = opb_ethernet_0_emac_intrpts PORT PHY_tx_er = opb_ethernet_0_PHY_tx_er PORT PHY_tx_en = opb_ethernet_0_PHY_tx_en PORT PHY_tx_data = opb_ethernet_0_PHY_tx_data PORT Freeze = net_gnd PORT IP2INTC_Irpt = opb_ethernet_0_IP2INTC_Irpt PORT PHY_Mii_clk = opb_ethernet_0_PHY_Mii_clk PORT PHY_Mii_data = opb_ethernet_0_PHY_Mii_data PORT PHY_col = opb_ethernet_0_PHY_col PORT PHY_crs = opb_ethernet_0_PHY_crs PORT PHY_dv = opb_ethernet_0_PHY_dv PORT PHY_rst_n = opb_ethernet_0_PHY_rst_n PORT PHY_tx_clk = opb_ethernet_0_PHY_tx_clk PORT PHY_rx_er =
opb_ethernet_0_PHY_rx_er END Steve
Kapp Senior Engineer Vanteon Corporation Office: (585) 248-0510, x289 www.vanteon.com
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