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AW: AW: AW: [microblaze-uclinux] Download problems (No target with id: -1)
> When I do it manually, i get following output on UART:
> -- Entering main() --
> Starting MemoryTest for DDR_SDRAM_64Mx32:
> Running 32-bit test...PASSED!
> Running 16-bit test...PASSED!
> Running 8-bit test...FAILED!
> -- Exiting main() --
>
> When i download the Bitstream through XPS, i receive passed for all
three tests.
That's a bit concerning. Check the implementation/system.par to make
sure you don't have any failed timing constraints.
------------------------------------------------------------------------
---
implementation/system.par file
------------------------------------------------------------------------
---
Release 8.1.02i par I.27
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
DE01002A:: Tue Sep 19 10:43:51 2006
par -w -ol high system_map.ncd system.ncd system.pcf
Constraints file: system.pcf.
Loading device for application Rf_Device from file '4vfx12.nph' in
environment D:\Programme\Xilinx\ISE.
"system" is an NCD, version 3.1, device xc4vfx12, package ff668,
speed -10
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to
85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260
Volts)
Device speed data version: "ADVANCED 1.58 2006-02-24".
Device Utilization Summary:
Number of BSCANs 1 out of 4 25%
Number of BUFGs 6 out of 32 18%
Number of DCM_ADVs 2 out of 4 50%
Number of DSP48s 3 out of 32 9%
Number of ILOGICs 69 out of 320 21%
Number of External IOBs 123 out of 320 38%
Number of LOCed IOBs 123 out of 123 100%
Number of OLOGICs 119 out of 320 37%
Number of RAMB16s 28 out of 36 77%
Number of Slices 2234 out of 5472 40%
Number of SLICEMs 449 out of 2736 16%
Overall effort level (-ol): High
Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 29 secs
Finished initial Timing Analysis. REAL time: 29 secs
Starting Placer
Phase 1.1
Phase 1.1 (Checksum:991d93) REAL time: 33 secs
Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 33 secs
Phase 3.2
.....
..........
Phase 3.2 (Checksum:98ae3a) REAL time: 1 mins 40 secs
Phase 4.30
Phase 4.30 (Checksum:26259fc) REAL time: 1 mins 40 secs
Phase 5.3
Phase 5.3 (Checksum:2faf07b) REAL time: 1 mins 41 secs
Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 1 mins 41 secs
Phase 7.8
...................................................
.................
.......................................................
.......................
..............
........
Phase 7.8 (Checksum:98e9ce) REAL time: 2 mins 52 secs
Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 2 mins 53 secs
Phase 10.18
Phase 10.18 (Checksum:5f5e0f6) REAL time: 3 mins 44 secs
Phase 11.27
Phase 11.27 (Checksum:68e7775) REAL time: 3 mins 50 secs
Phase 12.5
Phase 12.5 (Checksum:7270df4) REAL time: 3 mins 51 secs
Writing design to file system.ncd
Total REAL time to Placer completion: 4 mins 3 secs
Total CPU time to Placer completion: 3 mins 55 secs
Starting Router
Phase 1: 18624 unrouted; REAL time: 4 mins 5 secs
Phase 2: 15990 unrouted; REAL time: 4 mins 19 secs
Phase 3: 5663 unrouted; REAL time: 4 mins 34 secs
Phase 4: 5663 unrouted; (242) REAL time: 4 mins 36 secs
Phase 5: 5676 unrouted; (0) REAL time: 4 mins 40 secs
Phase 6: 5676 unrouted; (0) REAL time: 4 mins 42 secs
Phase 7: 0 unrouted; (0) REAL time: 5 mins
Phase 8: 0 unrouted; (0) REAL time: 5 mins 17 secs
Phase 9: 0 unrouted; (0) REAL time: 5 mins 44 secs
Total REAL time to Router completion: 5 mins 44 secs
Total CPU time to Router completion: 5 mins 28 secs
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------
------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max
Delay(ns)|
+---------------------+--------------+------+------+------------+-------
------+
| dlmb_port_BRAM_Clk | BUFGCTRL_X0Y0| No | 1357 | 0.274 | 2.635
|
+---------------------+--------------+------+------+------------+-------
------+
| ddr_dev_clk_s | BUFGCTRL_X0Y2| No | 189 | 0.130 | 2.649
|
+---------------------+--------------+------+------+------------+-------
------+
| ddr_clk_90_s |BUFGCTRL_X0Y24| No | 111 | 0.067 | 2.600
|
+---------------------+--------------+------+------+------------+-------
------+
| ddr_dev_clk_90_s |BUFGCTRL_X0Y11| No | 10 | 0.065 | 2.587
|
+---------------------+--------------+------+------+------------+-------
------+
| DBG_CLK_s | BUFGCTRL_X0Y1| No | 112 | 0.163 | 2.537
|
+---------------------+--------------+------+------+------------+-------
------+
|debug_module/bscan_u | | | | |
|
| pdate | Local| | 1 | 0.000 | 0.559
|
+---------------------+--------------+------+------+------------+-------
------+
|opb_intc_0/opb_intc_ | | | | |
|
|0/INTC_CORE_I/INTR_D | | | | |
|
| ET_I/interrupts<0> | Local| | 1 | 0.000 | 0.689
|
+---------------------+--------------+------+------+------------+-------
------+
|opb_intc_0/opb_intc_ | | | | |
|
|0/INTC_CORE_I/INTR_D | | | | |
|
| ET_I/interrupts<1> | Local| | 1 | 0.000 | 0.686
|
+---------------------+--------------+------+------+------------+-------
------+
|DCM_AUTOCALIBRATION_ | | | | |
|
|dcm_0/dcm_0/DCM_ADV_ | | | | |
|
|INST/dcm_0/dcm_0/DCM | | | | |
|
| _ADV_INST/clk(7) | Local| | 6 | 0.388 | 0.898
|
+---------------------+--------------+------+------+------------+-------
------+
|DCM_AUTOCALIBRATION_ | | | | |
|
|dcm_0/dcm_0/DCM_ADV_ | | | | |
|
|INST/dcm_0/dcm_0/DCM | | | | |
|
| _ADV_INST/ring(1) | Local| | 2 | 0.000 | 0.488
|
+---------------------+--------------+------+------+------------+-------
------+
|DCM_AUTOCALIBRATION_ | | | | |
|
|dcm_0/dcm_0/DCM_ADV_ | | | | |
|
|INST/dcm_0/dcm_0/DCM | | | | |
|
| _ADV_INST/clk(1) | Local| | 2 | 0.000 | 0.473
|
+---------------------+--------------+------+------+------------+-------
------+
|DCM_AUTOCALIBRATION_ | | | | |
|
|dcm_0/dcm_0/DCM_ADV_ | | | | |
|
|INST/dcm_0/dcm_0/DCM | | | | |
|
| _ADV_INST/clk(2) | Local| | 2 | 0.000 | 0.772
|
+---------------------+--------------+------+------+------------+-------
------+
|DCM_AUTOCALIBRATION_ | | | | |
|
|dcm_0/dcm_0/DCM_ADV_ | | | | |
|
|INST/dcm_0/dcm_0/DCM | | | | |
|
| _ADV_INST/clk(3) | Local| | 2 | 0.000 | 0.436
|
+---------------------+--------------+------+------+------------+-------
------+
|DCM_AUTOCALIBRATION_ | | | | |
|
|dcm_0/dcm_0/DCM_ADV_ | | | | |
|
|INST/dcm_0/dcm_0/DCM | | | | |
|
| _ADV_INST/clk(4) | Local| | 2 | 0.000 | 0.693
|
+---------------------+--------------+------+------+------------+-------
------+
|DCM_AUTOCALIBRATION_ | | | | |
|
|dcm_0/dcm_0/DCM_ADV_ | | | | |
|
|INST/dcm_0/dcm_0/DCM | | | | |
|
| _ADV_INST/clk(5) | Local| | 2 | 0.000 | 0.483
|
+---------------------+--------------+------+------+------------+-------
------+
|DCM_AUTOCALIBRATION_ | | | | |
|
|dcm_0/dcm_0/DCM_ADV_ | | | | |
|
|INST/dcm_0/dcm_0/DCM | | | | |
|
| _ADV_INST/clk(6) | Local| | 2 | 0.000 | 0.912
|
+---------------------+--------------+------+------+------------+-------
------+
|DCM_AUTOCALIBRATION_ | | | | |
|
|dcm_1/dcm_1/DCM_ADV_ | | | | |
|
|INST/dcm_1/dcm_1/DCM | | | | |
|
| _ADV_INST/clk(7) | Local| | 6 | 0.225 | 0.708
|
+---------------------+--------------+------+------+------------+-------
------+
|DCM_AUTOCALIBRATION_ | | | | |
|
|dcm_1/dcm_1/DCM_ADV_ | | | | |
|
|INST/dcm_1/dcm_1/DCM | | | | |
|
| _ADV_INST/clk(2) | Local| | 2 | 0.000 | 0.724
|
+---------------------+--------------+------+------+------------+-------
------+
|DCM_AUTOCALIBRATION_ | | | | |
|
|dcm_1/dcm_1/DCM_ADV_ | | | | |
|
|INST/dcm_1/dcm_1/DCM | | | | |
|
| _ADV_INST/clk(1) | Local| | 2 | 0.000 | 0.870
|
+---------------------+--------------+------+------+------------+-------
------+
|DCM_AUTOCALIBRATION_ | | | | |
|
|dcm_1/dcm_1/DCM_ADV_ | | | | |
|
|INST/dcm_1/dcm_1/DCM | | | | |
|
| _ADV_INST/ring(1) | Local| | 2 | 0.000 | 0.488
|
+---------------------+--------------+------+------+------------+-------
------+
|DCM_AUTOCALIBRATION_ | | | | |
|
|dcm_1/dcm_1/DCM_ADV_ | | | | |
|
|INST/dcm_1/dcm_1/DCM | | | | |
|
| _ADV_INST/clk(3) | Local| | 2 | 0.000 | 0.732
|
+---------------------+--------------+------+------+------------+-------
------+
|DCM_AUTOCALIBRATION_ | | | | |
|
|dcm_1/dcm_1/DCM_ADV_ | | | | |
|
|INST/dcm_1/dcm_1/DCM | | | | |
|
| _ADV_INST/clk(4) | Local| | 2 | 0.000 | 0.877
|
+---------------------+--------------+------+------+------------+-------
------+
|DCM_AUTOCALIBRATION_ | | | | |
|
|dcm_1/dcm_1/DCM_ADV_ | | | | |
|
|INST/dcm_1/dcm_1/DCM | | | | |
|
| _ADV_INST/clk(5) | Local| | 2 | 0.000 | 0.709
|
+---------------------+--------------+------+------+------------+-------
------+
|DCM_AUTOCALIBRATION_ | | | | |
|
|dcm_1/dcm_1/DCM_ADV_ | | | | |
|
|INST/dcm_1/dcm_1/DCM | | | | |
|
| _ADV_INST/clk(6) | Local| | 2 | 0.000 | 0.894
|
+---------------------+--------------+------+------+------------+-------
------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
The Delay Summary Report
The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
The AVERAGE CONNECTION DELAY for this design is: 1.383
The MAXIMUM PIN DELAY IS: 5.492
The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 4.551
Listing Pin Delays by value: (nsec)
d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 6.00 d >= 6.00
--------- --------- --------- --------- --------- ---------
6854 7032 3818 343 106 0
Timing Score: 0
Number of Timing Constraints that were not applied: 1
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
------------------------------------------------------------------------
------------------------------
Constraint | Requested | Actual |
Logic | Absolute |Number of
| | |
Levels | Slack |errors
------------------------------------------------------------------------
------------------------------
TS_dcm_0_dcm_0_CLK90_BUF = PERIOD TIMEGRP | 10.000ns | 9.912ns |
1 | 0.088ns | 0
"dcm_0_dcm_0_CLK90_BUF" TS_sys_c | | |
| |
lk_pin PHASE 2.5 ns HIGH 50% | | |
| |
------------------------------------------------------------------------
------------------------------
TS_dcm_0_dcm_0_CLK0_BUF = PERIOD TIMEGRP | 10.000ns | 9.216ns |
0 | 0.784ns | 0
"dcm_0_dcm_0_CLK0_BUF" TS_sys_clk_pin | | |
| |
HIGH 50% | | |
| |
------------------------------------------------------------------------
------------------------------
TS_dcm_0_dcm_0_CLKDV_BUF = PERIOD TIMEGRP | 15.000ns | 12.562ns |
8 | 2.438ns | 0
"dcm_0_dcm_0_CLKDV_BUF" TS_sys_c | | |
| |
lk_pin * 1.5 HIGH 50% | | |
| |
------------------------------------------------------------------------
------------------------------
TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | N/A | N/A |
N/A | N/A | N/A
pin" 10 ns HIGH 50% | | |
| |
------------------------------------------------------------------------
------------------------------
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that
the
constraint does not cover any paths or that it has no requested
value.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 6 mins 24 secs
Total CPU time to PAR completion: 6 mins
Peak Memory Usage: 265 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 0
Writing design to file system.ncd
PAR done!
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