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[microblaze-uclinux] Two SRAM EMC

To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: [microblaze-uclinux] Two SRAM EMC
From: "Bruno Herrera" <bruherrera@xxxxxxxxx>
Date: Thu, 30 Nov 2006 11:43:32 -0200
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Reply-to: microblaze-uclinux@xxxxxxxxxxxxxx
Sender: owner-microblaze-uclinux@xxxxxxxxxxxxxx
Hello all,

I got ucLinux running in my board but I until now I only can access
one EMC SRam. I would like to know how to get access to the second
SRAM EMC. Once ucLinux-auto only configure the main memory.

You can see may MSS an MSH bellow


-----------------------------------------------------------------

PARAMETER VERSION = 2.1.0


PORT opb_uartlite_0_RX = opb_uartlite_0_RX, DIR = IN
PORT opb_uartlite_0_TX = opb_uartlite_0_TX, DIR = OUT
PORT ssram_bank_0_addr = ssram_bank_0_addr, VEC = [0:19], DIR = OUT
PORT ssram_bank_0_ben = ssram_bank_0_ben, VEC = [0:3], DIR = O
PORT ssram_bank_0_cen = ssram_bank_0_cen, DIR = O
PORT ssram_bank_0_data = ssram_bank_0_data, VEC = [0:31], DIR = INOUT
PORT ssram_bank_0_rnw = ssram_bank_0_rnw, DIR = O
PORT ssram_bank_1_addr = ssram_bank_1_addr, VEC = [0:19], DIR = OUT
PORT ssram_bank_1_ben = ssram_bank_1_ben, VEC = [0:3], DIR = O
PORT ssram_bank_1_cen = ssram_bank_1_cen, DIR = O
PORT ssram_bank_1_clk = sys_clk, DIR = OUT, SIGIS = CLK
PORT ssram_bank_1_data = ssram_bank_1_data, VEC = [0:31], DIR = INOUT
PORT ssram_bank_1_rnw = ssram_bank_1_rnw, DIR = O
PORT sys_rst_s = sys_rst_s, DIR = IN
PORT ssram_bank_0_clk = sys_clk, DIR = OUT, SIGIS = CLK
PORT sys_clk = sys_clk, DIR = IN, SIGIS = CLK


# PORT RTS = net_gnd, DIR = IN
BEGIN util_bus_split
PARAMETER INSTANCE = addr_adj_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE_IN = 32
PARAMETER C_LEFT_POS = 10
PARAMETER C_SPLIT = 30
PORT Sig = ssram_bank_0_addr_full
PORT Out1 = ssram_bank_0_addr
END

BEGIN opb_emc
PARAMETER INSTANCE = ssram_bank_1
PARAMETER HW_VER = 2.00.a
# PARAMETER C_MEM1_BASEADDR = 0x20000000
# PARAMETER C_MEM1_HIGHADDR = 0x200fffff
PARAMETER C_NUM_BANKS_MEM = 1
PARAMETER C_MEM0_WIDTH = 32
PARAMETER C_SYNCH_MEM_0 = 1
PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
PARAMETER C_SYNCH_PIPEDELAY_0 = 2
PARAMETER C_MEM0_BASEADDR = 0xFF000000
PARAMETER C_MEM0_HIGHADDR = 0xff3fffff
PARAMETER C_INCLUDE_BURST = 1
BUS_INTERFACE SOPB = mb_opb
PORT Mem_BEN = ssram_bank_1_ben
PORT Mem_CEN = ssram_bank_1_cen
PORT Mem_DQ = ssram_bank_1_data
PORT Mem_RNW = ssram_bank_1_rnw
PORT Mem_A = ssram_bank_1_addr_full
PORT OPB_Clk = sys_clk
END

BEGIN opb_emc
PARAMETER INSTANCE = ssram_bank_0
PARAMETER HW_VER = 2.00.a
# PARAMETER C_MEM1_BASEADDR = 0xe8000000
# PARAMETER C_MEM1_HIGHADDR = 0xe80fffff
PARAMETER C_NUM_BANKS_MEM = 1
PARAMETER C_MEM0_WIDTH = 32
PARAMETER C_SYNCH_MEM_0 = 1
PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
PARAMETER C_SYNCH_PIPEDELAY_0 = 2
PARAMETER C_MEM0_BASEADDR = 0xF0000000
PARAMETER C_MEM0_HIGHADDR = 0xf03fffff
PARAMETER C_INCLUDE_BURST = 1
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk
PORT Mem_A = ssram_bank_0_addr_full
PORT Mem_DQ = ssram_bank_0_data
PORT Mem_RNW = ssram_bank_0_rnw
PORT Mem_BEN = ssram_bank_0_ben
PORT Mem_CEN = ssram_bank_0_cen
END

BEGIN opb_v20
PARAMETER INSTANCE = mb_opb
PARAMETER HW_VER = 1.10.b
PORT OPB_Clk = sys_clk
PORT SYS_Rst = sys_rst_s
END

BEGIN opb_uartlite
PARAMETER INSTANCE = console_uart
PARAMETER HW_VER = 1.00.b
PARAMETER C_CLK_FREQ = 50_000_000
PARAMETER C_BAUDRATE = 9600
PARAMETER C_USE_PARITY = 0
PARAMETER C_DATA_BITS = 8
PARAMETER C_BASEADDR = 0xFFFF2000
PARAMETER C_HIGHADDR = 0xffff20ff
BUS_INTERFACE SOPB = mb_opb
PORT Interrupt = uart_interrupt
PORT OPB_Clk = sys_clk
PORT RX = opb_uartlite_0_RX
PORT TX = opb_uartlite_0_TX
END

BEGIN opb_timer
PARAMETER INSTANCE = system_timer
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0xffff1000
PARAMETER C_HIGHADDR = 0xffff10ff
BUS_INTERFACE SOPB = mb_opb
PORT Freeze = net_gnd
PORT Interrupt = timer_interrupt
PORT OPB_Clk = sys_clk
END

BEGIN opb_mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 2.00.a
# PARAMETER C_USE_UART = 1
# PARAMETER C_UART_WIDTH = 8
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_WRITE_FSL_PORTS = 1
PARAMETER C_BASEADDR = 0xffff7000
PARAMETER C_HIGHADDR = 0xffff70ff
BUS_INTERFACE MFSL0 = donwload_link
BUS_INTERFACE SOPB = mb_opb
PORT DBG_CLK_0 = DBG_CLK_s
PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
PORT Interrupt = opb_mdm_interrupt
PORT OPB_Clk = sys_clk
PORT DBG_REG_EN_0 = DBG_REG_EN_s
PORT DBG_TDI_0 = DBG_TDI_s
PORT DBG_TDO_0 = DBG_TDO_s
PORT DBG_UPDATE_0 = DBG_UPDATE_s
END

BEGIN opb_intc
PARAMETER INSTANCE = system_intc
PARAMETER HW_VER = 1.00.c
PARAMETER C_BASEADDR = 0xffff3000
PARAMETER C_HIGHADDR = 0xffff30ff
BUS_INTERFACE SOPB = mb_opb
PORT Irq = opb_intc_0_Irq
PORT Intr = uart_interrupt & timer_interrupt
PORT OPB_Clk = sys_clk
END

BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 3.00.a
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_NUMBER_OF_PC_BRK = 2
PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
PARAMETER C_ICACHE_BASEADDR = 0xFF000000
PARAMETER C_ICACHE_HIGHADDR = 0xFF3FFFFF
PARAMETER C_DCACHE_BASEADDR = 0xFF000000
PARAMETER C_DCACHE_HIGHADDR = 0xFF3FFFFF
PARAMETER C_FSL_LINKS = 1
PARAMETER C_ADDR_TAG_BITS = 6
PARAMETER C_CACHE_BYTE_SIZE = 16384
PARAMETER C_USE_BARREL = 1
PARAMETER C_USE_DIV = 1
PARAMETER C_USE_MSR_INSTR = 1
PARAMETER C_USE_ICACHE = 1
PARAMETER C_USE_DCACHE = 1
PARAMETER C_DCACHE_ADDR_TAG = 6
PARAMETER C_DCACHE_BYTE_SIZE = 16384
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DOPB = mb_opb
BUS_INTERFACE IOPB = mb_opb
BUS_INTERFACE SFSL0 = donwload_link
PORT DBG_CLK = DBG_CLK_s
PORT CLK = sys_clk
PORT INTERRUPT = opb_intc_0_Irq
PORT DBG_CAPTURE = DBG_CAPTURE_s
PORT DBG_REG_EN = DBG_REG_EN_s
PORT DBG_UPDATE = DBG_UPDATE_s
PORT DBG_TDO = DBG_TDO_s
PORT DBG_TDI = DBG_TDI_s
END

BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk
PORT SYS_Rst = sys_rst_s
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_bram_if_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00003fff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk
PORT SYS_Rst = sys_rst_s
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_bram_if_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00003fff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN bram_block
PARAMETER INSTANCE = bram_block_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_MEMSIZE = 16384
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END

BEGIN fsl_v20
PARAMETER INSTANCE = donwload_link
PARAMETER HW_VER = 2.00.a
PORT FSL_Clk = sys_clk
PORT SYS_Rst = sys_rst_s
END

BEGIN util_bus_split
PARAMETER INSTANCE = addr_adj_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE_IN = 32
PARAMETER C_LEFT_POS = 10
PARAMETER C_SPLIT = 30
PORT Sig = ssram_bank_1_addr_full
PORT Out1 = ssram_bank_1_addr
END




--------------------------------------------------------------------


PARAMETER VERSION = 2.2.0


BEGIN OS
PARAMETER OS_NAME = uclinux
PARAMETER OS_VER = 1.00.d
PARAMETER PROC_INSTANCE = microblaze_0
PARAMETER stdout = console_uart
PARAMETER stdin = console_uart
PARAMETER main_memory = ssram_bank_1
PARAMETER main_memory_size = 0x00400000
PARAMETER main_memory_start = 0xFF000000
PARAMETER lmb_memory = ilmb_bram_if_cntlr
PARAMETER main_memory_bank = 0
PARAMETER TARGET_DIR = RC200
END


BEGIN PROCESSOR
PARAMETER DRIVER_NAME = cpu
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = microblaze_0
PARAMETER COMPILER = mb-gcc
PARAMETER ARCHIVER = mb-ar
PARAMETER CORE_CLOCK_FREQ_HZ = 50000000
END


BEGIN DRIVER
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 1.00.b
PARAMETER HW_INSTANCE = console_uart
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ilmb_bram_if_cntlr
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = dlmb_bram_if_cntlr
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = emc
PARAMETER DRIVER_VER = 2.00.a
PARAMETER HW_INSTANCE = ssram_bank_0
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = emc
PARAMETER DRIVER_VER = 2.00.a
PARAMETER HW_INSTANCE = ssram_bank_1
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 1.00.b
PARAMETER HW_INSTANCE = debug_module
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = intc
PARAMETER DRIVER_VER = 1.00.c
PARAMETER HW_INSTANCE = system_intc
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = tmrctr
PARAMETER DRIVER_VER = 1.00.b
PARAMETER HW_INSTANCE = system_timer
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = opbarb
PARAMETER DRIVER_VER = 1.02.a
PARAMETER HW_INSTANCE = mb_opb
END




--
Bruno Meirelles Herrera
Eng. de Computação / Computer Eng.

SCJP -Sun Certified Programmer for Java 2 Platform 1.4
SCJA -  Sun Certified Associate for Java Platform

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