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Re: [microblaze-uclinux] Kernel freezes at "Calibrating delay loop..."

To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: Re: [microblaze-uclinux] Kernel freezes at "Calibrating delay loop..."
From: David McCullough <david_mccullough@xxxxxxxxxxxxxxxxxxxxxx>
Date: Tue, 12 Dec 2006 09:16:33 +1000
In-reply-to: <457DCDD6.5040603@xxxxxxxxxxxxxxxxxx>
References: <457DCDD6.5040603@xxxxxxxxxxxxxxxxxx>
Reply-to: microblaze-uclinux@xxxxxxxxxxxxxx
Sender: owner-microblaze-uclinux@xxxxxxxxxxxxxx
User-agent: Mutt/1.5.11
Jivin Christian Schleiffer lays it down ...
> Hi,
> 
> currently I'm trying to make a MB design work on a Suzaku SZ030 [1]
> module. My uClinux image freezes after it has displayed the message
> "Calibrating delay loop...".
> Google told me that I probably have a problem with my timer.

You need working interrupts, context switched and a working timer to
generate the interrupts to get past the bogomips line.  It one of the
first true tests to bringing up a platform :-)

> I briefly
> checked the source codes and temporarily removed the bogoMIPS
> calculation in init/main.c. This kernel image now freezes at "Setting up
> interface lo:"
> 
> Any suggestions how to fix that problem? I think I will dive deeper into
> the kernel code tomorrow... add some debugging output and try to find
> the exact point where it freezes. But I would appreciate, if anybody has
> a better idea ;)

Get the timer/interrupts/whatever working,  you have to anyway,

Cheers,
Davidm


> I'm working with ISE/EDK 8.2i (all patches applied).
> This is my bootlog:
> 
> > BBoot v2.1 (microblaze)
> > Press 'z' or 'Z' for BBoot Menu.
> > Hermit-At v1.1.3 (suzaku/microblaze) compiled at 13:49:17, Aug 15 2006
> > hermit> b
> >
> > Copying  kernel............................done.
> > Linux version 2.4.32-uc0 (atmark@atde) (gcc version 3.4.1 ( Xilinx EDK 8.1 Build
> >  EDK_I.17 090206 )) #2 2006Ç¯ 10·î 19Æü ÌÚÍËÆü 11:32:49 JST
> > On node 0 totalpages: 4096
> > zone(0): 4096 pages.
> > zone(1): 0 pages.
> > zone(2): 0 pages.
> > CPU: MICROBLAZE
> > Kernel command line:
> > Console: xmbserial on UARTLite
> > Calibrating delay loop...
> 
> Thanks in advance
> Cheers
> /Chris
> 
> 
> [1] http://suzaku-en.atmark-techno.com/series/suzaku-s

> 
>  PARAMETER VERSION = 2.2.0
> 
> 
> BEGIN OS
>  PARAMETER OS_NAME = standalone
>  PARAMETER OS_VER = 1.00.a
>  PARAMETER PROC_INSTANCE = microblaze_i
>  PARAMETER stdout = console_uart
>  PARAMETER stdin = console_uart
> END
> 
> 
> BEGIN PROCESSOR
>  PARAMETER DRIVER_NAME = cpu
>  PARAMETER DRIVER_VER = 1.01.a
>  PARAMETER HW_INSTANCE = microblaze_i
> END
> 
> 
> BEGIN DRIVER
>  PARAMETER DRIVER_NAME = uartlite
>  PARAMETER DRIVER_VER = 1.01.a
>  PARAMETER HW_INSTANCE = console_uart
> END
> 
> BEGIN DRIVER
>  PARAMETER DRIVER_NAME = generic
>  PARAMETER DRIVER_VER = 1.00.a
>  PARAMETER HW_INSTANCE = d_lmb_bram_if_cntlr
> END
> 
> BEGIN DRIVER
>  PARAMETER DRIVER_NAME = generic
>  PARAMETER DRIVER_VER = 1.00.a
>  PARAMETER HW_INSTANCE = d_opb_v20
> END
> 
> BEGIN DRIVER
>  PARAMETER DRIVER_NAME = generic
>  PARAMETER DRIVER_VER = 1.00.a
>  PARAMETER HW_INSTANCE = i_lmb_bram_if_cntlr
> END
> 
> BEGIN DRIVER
>  PARAMETER DRIVER_NAME = generic
>  PARAMETER DRIVER_VER = 1.00.a
>  PARAMETER HW_INSTANCE = sdram_controller
> END
> 
> BEGIN DRIVER
>  PARAMETER DRIVER_NAME = generic
>  PARAMETER DRIVER_VER = 1.00.a
>  PARAMETER HW_INSTANCE = system_memcon
> END
> 
> BEGIN DRIVER
>  PARAMETER DRIVER_NAME = tmrctr
>  PARAMETER DRIVER_VER = 1.00.b
>  PARAMETER HW_INSTANCE = system_timer
> END
> 
> BEGIN DRIVER
>  PARAMETER DRIVER_NAME = gpio
>  PARAMETER DRIVER_VER = 2.01.a
>  PARAMETER HW_INSTANCE = opb_gpio_0
> END
> 
> BEGIN DRIVER
>  PARAMETER DRIVER_NAME = gpio
>  PARAMETER DRIVER_VER = 2.01.a
>  PARAMETER HW_INSTANCE = led_gpio
> END
> 
> BEGIN DRIVER
>  PARAMETER DRIVER_NAME = intc
>  PARAMETER DRIVER_VER = 1.00.c
>  PARAMETER HW_INSTANCE = system_intc
> END
> 
> BEGIN DRIVER
>  PARAMETER DRIVER_NAME = uartlite
>  PARAMETER DRIVER_VER = 1.01.a
>  PARAMETER HW_INSTANCE = extension_uart
> END
> 
> 

> 
> 
>  PARAMETER VERSION = 2.1.0
> 
> 
>  PORT SYS_RST_IN = SYS_RST_IN, DIR = I
>  PORT SYS_CLK_IN = SYS_CLK_IN, DIR = I, SIGIS = CLK, CLK_FREQ = 3.6864
>  PORT SYS_CLK_OUT = SYS_CLK, DIR = O
>  PORT RAM_CLK = RAM_CLK, DIR = I
>  PORT LA = LA, VEC = [0:22], DIR = O
>  PORT LD = LD, VEC = [0:15], DIR = IO
>  PORT RAM_DQM = SDRAM_DQM, VEC = [0:1], DIR = O
>  PORT RAM_BS = SDRAM_BS, VEC = [0:1], DIR = O
>  PORT RAM_CSn = SDRAM_CSn, DIR = O
>  PORT RAM_RASn = SDRAM_RASn, DIR = O
>  PORT RAM_CASn = SDRAM_CASn, DIR = O
>  PORT RAM_WEn = SDRAM_WEn, DIR = O
>  PORT RAM_CKE = SDRAM_CKE, DIR = O
>  PORT FLASH_CEn = FLASH_CEn, DIR = O
>  PORT FLASH_OEn = FLASH_OEn, DIR = O
>  PORT FLASH_WEn = FLASH_WEn, DIR = O
>  PORT FLASH_BYTEn = FLASH_BYTEn, DIR = O
>  PORT FLASH_RnB = FLASH_RnB, DIR = I
>  PORT MAC_AEN = MAC_AEN, DIR = O
>  PORT MAC_WRn = MAC_WRn, DIR = O
>  PORT MAC_RDn = MAC_RDn, DIR = O
>  PORT MAC_INTR = mac_interrupt, DIR = I, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH
>  PORT MAC_BEn = MAC_BEn, DIR = O, VEC = [0:1]
>  PORT MAC_ARDY = MAC_ARDY, DIR = I
>  PORT MAC_ADSn = MAC_ADSn, DIR = O
>  PORT LEDn = LEDn, DIR = O
>  PORT CNSL_RX = CNSL_RX, DIR = I
>  PORT CNSL_TX = CNSL_TX, DIR = O
>  PORT BOOTMODE = BOOTMODE, DIR = I
>  PORT BUS_REL = BUS_REL, DIR = I
>  PORT BUS_REQ = BUS_REQ, DIR = O
>  PORT RESERVE_COLLECT = RESERVE_COLLECT, DIR = O
>  PORT FPGA_RESET_EN = FPGA_RESET_EN, DIR = IO
>  PORT microblaze_i_FSL0_S_CLK_pin = microblaze_i_FSL1_S_CLK, DIR = O, SIGIS = CLK
>  PORT microblaze_i_FSL0_S_READ_pin = microblaze_i_FSL1_S_READ, DIR = O
>  PORT microblaze_i_FSL0_S_DATA_pin = microblaze_i_FSL1_S_DATA, DIR = I, VEC = [0:31]
>  PORT microblaze_i_FSL0_S_EXISTS_pin = microblaze_i_FSL1_S_EXISTS, DIR = I
>  PORT microblaze_i_FSL0_M_CLK_pin = microblaze_i_FSL1_M_CLK, DIR = O, SIGIS = CLK 
>  PORT microblaze_i_FSL0_M_WRITE_pin = microblaze_i_FSL1_M_WRITE, DIR = O
>  PORT microblaze_i_FSL0_M_DATA_pin = microblaze_i_FSL1_M_DATA, DIR = O, VEC = [0:31]
>  PORT microblaze_i_FSL0_M_FULL_pin = microblaze_i_FSL1_M_FULL, DIR = I
>  PORT EXT_RX = EXT_RX, DIR = I
>  PORT EXT_TX = EXT_TX, DIR = O
> 
> 
> BEGIN opb_timer
>  PARAMETER INSTANCE = system_timer
>  PARAMETER HW_VER = 1.00.b
>  PARAMETER C_BASEADDR = 0xFFFF1000
>  PARAMETER C_HIGHADDR = 0xFFFF10FF
>  BUS_INTERFACE SOPB = d_opb_v20
>  PORT OPB_Clk = SYS_CLK
>  PORT Interrupt = timer_interrupt
> END
> 
> BEGIN opb_emc_w
>  PARAMETER INSTANCE = system_memcon
>  PARAMETER HW_VER = 1.00.a
>  PARAMETER C_BASEADDR = 0xFFFF0000
>  PARAMETER C_HIGHADDR = 0xFFFF01FF
>  PARAMETER C_NUM_BANKS_MEM = 2
>  PARAMETER C_OPB_CLK_PERIOD_PS = 19376
>  PARAMETER C_MEM0_BASEADDR = 0xFFE0_0000
>  PARAMETER C_MEM0_HIGHADDR = 0xFFEF_FFFF
>  PARAMETER C_MEM1_BASEADDR = 0xFF00_0000
>  PARAMETER C_MEM1_HIGHADDR = 0xFF7F_FFFF
>  PARAMETER C_MEM0_WIDTH = 16
>  PARAMETER C_MEM1_WIDTH = 16
>  PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 0
>  PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_1 = 0
>  PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_0 = 45000
>  PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_0 = 35000
>  PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_0 = 35000
>  PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_0 = 45000
>  PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_0 = 35000
>  PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_0 = 0
>  PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_0 = 0
>  PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_1 = 40000
>  PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_1 = 40000
>  PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_1 = 40000
>  PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_1 = 40000
>  PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_1 = 40000
>  PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_1 = 0
>  PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_1 = 0
>  PARAMETER C_MAX_MEM_WIDTH = 16
>  BUS_INTERFACE SOPB = d_opb_v20
>  PORT OPB_Clk = SYS_CLK
>  PORT Mem_A = MEMCON_ADR
>  PORT Mem_OEN = MEMCON_OEn
>  PORT Mem_WEN = MEMCON_WEn
>  PORT Mem_CEN = MEMCON_CEn
>  PORT Mem_BEN = MEMCON_BEn
>  PORT Mem_DQ_O = MEMCON_DQ_O
>  PORT Mem_DQ_I = MEMCON_DQ_I
>  PORT Mem_DQ_T = MEMCON_DQ_T
> END
> 
> BEGIN opb_intc
>  PARAMETER INSTANCE = system_intc
>  PARAMETER HW_VER = 1.00.c
>  PARAMETER C_BASEADDR = 0xFFFF3000
>  PARAMETER C_HIGHADDR = 0xFFFF30FF
>  PARAMETER C_NUM_INTR_INPUTS = 3
>  BUS_INTERFACE SOPB = d_opb_v20
>  PORT Irq = interrupt
> # PORT Intr = mac_interrupt &extension_uart_Interrupt& console_uart_interrupt & timer_interrupt
>  PORT Intr = extension_uart_Interrupt & mac_interrupt& console_uart_interrupt & timer_interrupt
> END
> 
> BEGIN opb_sdram_w
>  PARAMETER INSTANCE = sdram_controller
>  PARAMETER HW_VER = 1.00.a
>  PARAMETER C_INCLUDE_BURST_SUPPORT = 1
>  PARAMETER C_INCLUDE_HIGHSPEED_PIPE = 1
>  PARAMETER C_SDRAM_TMRD = 2
>  PARAMETER C_SDRAM_TWR = 15000
>  PARAMETER C_SDRAM_TCCD = 1
>  PARAMETER C_SDRAM_TRAS = 45000
>  PARAMETER C_SDRAM_TRC = 65000
>  PARAMETER C_SDRAM_TRFC = 75000
>  PARAMETER C_SDRAM_TRCD = 20000
>  PARAMETER C_SDRAM_TRRD = 15000
>  PARAMETER C_SDRAM_TRP = 20000
>  PARAMETER C_SDRAM_TREF = 64
>  PARAMETER C_SDRAM_REFRESH_NUMROWS = 4096
>  PARAMETER C_SDRAM_CAS_LAT = 2
>  PARAMETER C_SDRAM_DWIDTH = 16
>  PARAMETER C_SDRAM_AWIDTH = 12
>  PARAMETER C_SDRAM_COL_AWIDTH = 9
>  PARAMETER C_SDRAM_BANK_AWIDTH = 2
>  PARAMETER C_SDRAM_TREFI = 7812500
>  PARAMETER C_OPB_CLK_PERIOD_PS = 19376
>  PARAMETER C_BASEADDR = 0x80000000
>  PARAMETER C_HIGHADDR = 0x80FFFFFF
>  BUS_INTERFACE SOPB = d_opb_v20
>  PORT SDRAM_CASn = SDRAM_CASn
>  PORT SDRAM_WEn = SDRAM_WEn
>  PORT SDRAM_Clk_in = SYS_CLK
>  PORT SDRAM_DQM = SDRAM_DQM
>  PORT SDRAM_CSn = SDRAM_CSn
>  PORT SDRAM_CKE = SDRAM_CKE
>  PORT OPB_Clk = SYS_CLK
>  PORT SDRAM_BankAddr = SDRAM_BS
>  PORT SDRAM_RASn = SDRAM_RASn
>  PORT SDRAM_Addr = SDRAM_ADR
>  PORT SDRAM_DQ_O = SDRAM_DQ_O
>  PORT SDRAM_DQ_I = SDRAM_DQ_I
>  PORT SDRAM_DQ_T = SDRAM_DQ_T
> END
> 
> BEGIN opb_gpio
>  PARAMETER INSTANCE = opb_gpio_0
>  PARAMETER HW_VER = 3.01.b
>  PARAMETER C_GPIO_WIDTH = 8
>  PARAMETER C_ALL_INPUTS = 0
>  PARAMETER C_IS_BIDIR = 0
>  PARAMETER C_BASEADDR = 0xFFFFA000
>  PARAMETER C_HIGHADDR = 0xFFFFA1FF
>  BUS_INTERFACE SOPB = d_opb_v20
>  PORT GPIO_in = GPIO_IO_0_I
>  PORT GPIO_d_out = GPIO_IO_0_O
> END
> 
> BEGIN microblaze
>  PARAMETER INSTANCE = microblaze_i
>  PARAMETER HW_VER = 4.00.b
>  PARAMETER C_USE_BARREL = 1
>  PARAMETER C_USE_DIV = 1
>  PARAMETER C_FSL_DATA_SIZE = 32
>  PARAMETER C_USE_ICACHE = 1
>  PARAMETER C_ICACHE_BASEADDR = 0x80000000
>  PARAMETER C_ICACHE_HIGHADDR = 0x80FFFFFF
>  PARAMETER C_USE_FPU = 0
>  PARAMETER C_USE_MSR_INSTR = 1
>  PARAMETER C_USE_PCMP_INSTR = 1
>  PARAMETER C_FPU_EXCEPTION = 0
>  PARAMETER C_DIV_ZERO_EXCEPTION = 0
>  PARAMETER C_DOPB_BUS_EXCEPTION = 0
>  PARAMETER C_IOPB_BUS_EXCEPTION = 0
>  PARAMETER C_ILL_OPCODE_EXCEPTION = 0
>  PARAMETER C_UNALIGNED_EXCEPTIONS = 0
>  PARAMETER C_USE_HW_MUL = 1
>  PARAMETER C_DEBUG_ENABLED = 0
>  PARAMETER C_FSL_LINKS = 2
>  BUS_INTERFACE DLMB = d_lmb_v10
>  BUS_INTERFACE ILMB = i_lmb_v10
>  BUS_INTERFACE DOPB = d_opb_v20
>  BUS_INTERFACE IOPB = d_opb_v20
>  PORT INTERRUPT = interrupt
>  PORT FSL1_S_CLK = microblaze_i_FSL1_S_CLK
>  PORT FSL1_S_READ = microblaze_i_FSL1_S_READ
>  PORT FSL1_S_DATA = microblaze_i_FSL1_S_DATA
>  PORT FSL1_S_EXISTS = microblaze_i_FSL1_S_EXISTS
>  PORT FSL1_M_CLK = microblaze_i_FSL1_M_CLK
>  PORT FSL1_M_WRITE = microblaze_i_FSL1_M_WRITE
>  PORT FSL1_M_DATA = microblaze_i_FSL1_M_DATA
>  PORT FSL1_M_FULL = microblaze_i_FSL1_M_FULL
> END
> 
> BEGIN opb_gpio
>  PARAMETER INSTANCE = led_gpio
>  PARAMETER HW_VER = 3.01.b
>  PARAMETER C_GPIO_WIDTH = 1
>  PARAMETER C_DOUT_DEFAULT = 0xffffffff
>  PARAMETER C_BASEADDR = 0xFFFFA200
>  PARAMETER C_HIGHADDR = 0xFFFFA3FF
>  BUS_INTERFACE SOPB = d_opb_v20
>  PORT GPIO_d_out = LEDn
> END
> 
> BEGIN lmb_v10
>  PARAMETER INSTANCE = i_lmb_v10
>  PARAMETER HW_VER = 1.00.a
>  PORT SYS_Rst = SYS_RST
>  PORT LMB_Clk = SYS_CLK
> END
> 
> BEGIN lmb_bram_if_cntlr
>  PARAMETER INSTANCE = i_lmb_bram_if_cntlr
>  PARAMETER HW_VER = 1.00.b
>  PARAMETER C_BASEADDR = 0x00000000
>  PARAMETER C_HIGHADDR = 0x00001fff
>  BUS_INTERFACE SLMB = i_lmb_v10
>  BUS_INTERFACE BRAM_PORT = conn_1
>  PORT LMB_Clk = SYS_CLK
> END
> 
> BEGIN opb_uartlite
>  PARAMETER INSTANCE = extension_uart
>  PARAMETER HW_VER = 1.00.b
>  PARAMETER C_BAUDRATE = 115200
>  PARAMETER C_USE_PARITY = 0
>  PARAMETER C_CLK_FREQ = 51609600
>  PARAMETER C_BASEADDR = 0xFFFF4000
>  PARAMETER C_HIGHADDR = 0xFFFF40FF
>  BUS_INTERFACE SOPB = d_opb_v20
>  PORT Interrupt = extension_uart_Interrupt
>  PORT RX = EXT_RX
>  PORT TX = EXT_TX
>  PORT OPB_Clk = SYS_CLK
> END
> 
> BEGIN dcm_module
>  PARAMETER INSTANCE = dcm_14_multi
>  PARAMETER HW_VER = 1.00.a
>  PARAMETER C_CLK0_BUF = FALSE
>  PARAMETER C_CLKIN_PERIOD = 271.267361
>  PARAMETER C_CLK_FEEDBACK = NONE
>  PARAMETER C_EXT_RESET_HIGH = 1
>  PARAMETER C_CLKFX_MULTIPLY = 14
>  PARAMETER C_CLKFX_BUF = TRUE
>  PARAMETER C_CLKIN_BUF = FALSE
>  PARAMETER C_DUTY_CYCLE_CORRECTION = FALSE
>  PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED
>  PORT CLKIN = SYS_CLK_IN
>  PORT RST = net_gnd
>  PORT CLKFX = SYS_CLK
> END
> 
> BEGIN opb_v20
>  PARAMETER INSTANCE = d_opb_v20
>  PARAMETER HW_VER = 1.10.c
>  PORT SYS_Rst = SYS_RST
>  PORT OPB_Clk = SYS_CLK
> END
> 
> BEGIN lmb_v10
>  PARAMETER INSTANCE = d_lmb_v10
>  PARAMETER HW_VER = 1.00.a
>  PORT SYS_Rst = SYS_RST
>  PORT LMB_Clk = SYS_CLK
> END
> 
> BEGIN lmb_bram_if_cntlr
>  PARAMETER INSTANCE = d_lmb_bram_if_cntlr
>  PARAMETER HW_VER = 1.00.b
>  PARAMETER C_BASEADDR = 0x00000000
>  PARAMETER C_HIGHADDR = 0x00001fff
>  BUS_INTERFACE SLMB = d_lmb_v10
>  BUS_INTERFACE BRAM_PORT = conn_0
>  PORT LMB_Clk = SYS_CLK
> END
> 
> BEGIN opb_uartlite
>  PARAMETER INSTANCE = console_uart
>  PARAMETER HW_VER = 1.00.b
>  PARAMETER C_DATA_BITS = 8
>  PARAMETER C_CLK_FREQ = 51609600
>  PARAMETER C_BAUDRATE = 115200
>  PARAMETER C_USE_PARITY = 0
>  PARAMETER C_ODD_PARITY = 1
>  PARAMETER C_BASEADDR = 0xFFFF2000
>  PARAMETER C_HIGHADDR = 0xFFFF20FF
>  BUS_INTERFACE SOPB = d_opb_v20
>  PORT OPB_Clk = SYS_CLK
>  PORT TX = CNSL_TX
>  PORT RX = CNSL_RX
>  PORT Interrupt = console_uart_interrupt
> END
> 
> BEGIN bus_select_s
>  PARAMETER INSTANCE = bus_select_s_0
>  PARAMETER HW_VER = 1.00.a
>  PARAMETER C_COMPATIBLE_32MBIT = 0
>  PORT SYS_RST_IN = SYS_RST_IN
>  PORT BUS_REL = BUS_REL
>  PORT SYS_RST = SYS_RST
>  PORT SDRAM_ADR = SDRAM_ADR
>  PORT SDRAM_DQ_O = SDRAM_DQ_O
>  PORT SDRAM_DQ_I = SDRAM_DQ_I
>  PORT SDRAM_DQ_T = SDRAM_DQ_T
>  PORT MEMCON_CEn = MEMCON_CEn
>  PORT MEMCON_ADR = MEMCON_ADR
>  PORT MEMCON_BEn = MEMCON_BEn
>  PORT MEMCON_WEn = MEMCON_WEn
>  PORT MEMCON_OEn = MEMCON_OEn
>  PORT MAC_AEN = MAC_AEN
>  PORT MAC_WRn = MAC_WRn
>  PORT MAC_RDn = MAC_RDn
>  PORT MAC_BEn = MAC_BEn
>  PORT MAC_ADSn = MAC_ADSn
>  PORT MEMCON_DQ_O = MEMCON_DQ_O
>  PORT MEMCON_DQ_I = MEMCON_DQ_I
>  PORT MEMCON_DQ_T = MEMCON_DQ_T
>  PORT LA = LA
>  PORT LD = LD
>  PORT FLASH_CEn = FLASH_CEn
>  PORT FLASH_OEn = FLASH_OEn
>  PORT FLASH_WEn = FLASH_WEn
>  PORT FLASH_BYTEn = FLASH_BYTEn
>  PORT GPIO_IO_0_O = GPIO_IO_0_O
>  PORT GPIO_IO_0_I = GPIO_IO_0_I
>  PORT BUS_REQ = BUS_REQ
>  PORT BOOTMODE = BOOTMODE
>  PORT FLASH_RnB = FLASH_RnB
>  PORT MAC_ARDY = MAC_ARDY
>  PORT RESERVE_COLLECT = RESERVE_COLLECT
>  PORT FPGA_RESET_EN = FPGA_RESET_EN
>  PORT RAM_CLK = RAM_CLK
> END
> 
> BEGIN bram_block
>  PARAMETER INSTANCE = bram_block_0
>  PARAMETER HW_VER = 1.00.a
>  PARAMETER C_MEMSIZE = 8192
>  BUS_INTERFACE PORTA = conn_0
>  BUS_INTERFACE PORTB = conn_1
> END
> 


-- 
David McCullough,  david_mccullough@xxxxxxxxxxxxxxxxxxx,   Ph:+61 734352815
Secure Computing - SnapGear  http://www.uCdot.org http://www.cyberguard.com
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