[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[microblaze-uclinux] FSL download doesn't work
Hi,
I'm using EDK 8.2.02 on a Windows machine with a parallel
programming cable. It seems I can't enable fast (FSL)
downloads (I _am_ able to download kernel image without
FSL, but that takes over 20 minutes).
Here's what xmd says:
XMD%
Loading XMP File..
Processor(s) in System ::
Microblaze(1) : microblaze_0
Address Map for Processor microblaze_0
(0x00000000-0x00001fff) dlmb_cntlr dlmb
(0x00000000-0x00001fff) ilmb_cntlr ilmb
(0x24000000-0x27ffffff) DDR_SDRAM_32Mx16 mb_opb
(0x24000000-0x27ffffff) DDR_SDRAM_32Mx16 ixcl
(0x24000000-0x27ffffff) DDR_SDRAM_32Mx16 dxcl
(0x40000000-0x4000ffff) LEDs_4Bit mb_opb
(0x40600000-0x4060ffff) RS232 mb_opb
(0x40c00000-0x40c0ffff) Ethernet_MAC mb_opb
(0x41200000-0x4120ffff) opb_intc_0 mb_opb
(0x41400000-0x4140ffff) debug_module mb_opb
(0x41c00000-0x41c0ffff) opb_timer_1 mb_opb
XMD% connect mb mdm -bscan USER1 -pfsl port 0 type s
Connecting to cable (Parallel Port - LPT1).
Checking cable driver.
Driver windrvr6.sys version = 7.0.0.0. LPT base address = 0378h.
ECP base address = FFFFFFFFh.
Cable connection established.
JTAG chain configuration
--------------------------------------------------
Device ID Code IR Length Part Name
1 0167c093 10 XC4VLX25
Assuming, Device No: 1 contains the MicroBlaze system
Connected to the JTAG MicroProcessor Debug Module (MDM)
No of processors = 1
MicroBlaze Processor 1 Configuration :
-------------------------------------
Version............................5.00.c
No of PC Breakpoints...............2
No of Read Addr/Data Watchpoints...0
No of Write Addr/Data Watchpoints..0
Instruction Cache Support..........on
Instruction Cache Base Address.....0x24000000
Instruction Cache High Address.....0x27ffffff
Data Cache Support.................on
Data Cache Base Address............0x24000000
Data Cache High Address............0x27ffffff
Exceptions Support................off
FPU Support.......................off
FSL DCache Support.................on
FSL ICache Support.................on
Hard Divider Support...............on
Hard Multiplier Support............on
Barrel Shifter Support.............on
MSR clr/set Instruction Support....on
Compare Instruction Support........on
Number of FSL ports..............1
PVR Supported......................on
PVR Configuration Type.............Full
PVR MicroBlaze Source Version......0x3
PVR MicroBlaze User1 ID............0x0
PVR MicroBlaze User2 ID............0x0
MBsfsl(0)-MDMmfsl(0) Connected..........Yes
JTAG MDM Connected to MicroBlaze 1
Connected to "mb" target. id = 0
Starting GDB server for "mb" target (id = 0) at TCP port no 1234
XMD% dow -data image.bin 0x24000000
And now the download takes a long time, as if xmd is ignoring
the FSL link. Any idea why this happens? (The MHS file is
attached.)
--
Ivan Stankovic, pokemon@xxxxxxxxxxxxxx
"Protect your digital freedom and privacy, eliminate DRM,
learn more at http://www.defectivebydesign.org/what_is_drm";
# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 8.2.02 Build EDK_Im_Sp2.4
# Fri Mar 09 15:32:55 2007
# Target Board: Memec Virtex-4 LC Development Board Rev 1
# Family: virtex4
# Device: XC4VLX25
# Package: SF363
# Speed Grade: -10
# Processor: Microblaze
# System clock frequency: 100.000000 MHz
# Debug interface: On-Chip HW Debug Module
# Data Cache: 16 KB
# Instruction Cache: 16 KB
# On Chip Memory : 8 KB
# Total Off Chip Memory : 64 MB
# - DDR_SDRAM_32Mx16 = 64 MB
# ##############################################################################
PARAMETER VERSION = 2.1.0
PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = I
PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = O
PORT fpga_0_RS232_req_to_send_pin = net_gnd, DIR = O
PORT fpga_0_LEDs_4Bit_GPIO_d_out_pin = fpga_0_LEDs_4Bit_GPIO_d_out, DIR = O, VEC = [0:3]
PORT fpga_0_DDR_SDRAM_32Mx16_DDR_Clk_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_Clk, DIR = O
PORT fpga_0_DDR_SDRAM_32Mx16_DDR_Clkn_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_Clkn, DIR = O
PORT fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_Addr, DIR = O, VEC = [0:12]
PORT fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr, DIR = O, VEC = [0:1]
PORT fpga_0_DDR_SDRAM_32Mx16_DDR_CASn_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_CASn, DIR = O
PORT fpga_0_DDR_SDRAM_32Mx16_DDR_CKE_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_CKE, DIR = O
PORT fpga_0_DDR_SDRAM_32Mx16_DDR_CSn_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_CSn, DIR = O
PORT fpga_0_DDR_SDRAM_32Mx16_DDR_RASn_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_RASn, DIR = O
PORT fpga_0_DDR_SDRAM_32Mx16_DDR_WEn_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_WEn, DIR = O
PORT fpga_0_DDR_SDRAM_32Mx16_DDR_DM_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_DM, DIR = O, VEC = [0:1]
PORT fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_DQS, DIR = IO, VEC = [0:1]
PORT fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_DQ, DIR = IO, VEC = [0:15]
PORT fpga_0_Ethernet_MAC_PHY_tx_er_pin = fpga_0_Ethernet_MAC_PHY_tx_er, DIR = O
PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk, DIR = I
PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk, DIR = I
PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs, DIR = I
PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv, DIR = I
PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data, DIR = I, VEC = [3:0]
PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col, DIR = I
PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er, DIR = I
PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en, DIR = O
PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data, DIR = O, VEC = [3:0]
PORT fpga_0_Ethernet_MAC_PHY_Mii_clk_pin = fpga_0_Ethernet_MAC_PHY_Mii_clk, DIR = IO
PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin = fpga_0_Ethernet_MAC_PHY_rst_n, DIR = O
PORT fpga_0_Ethernet_MAC_PHY_Mii_data_pin = fpga_0_Ethernet_MAC_PHY_Mii_data, DIR = IO
PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 5.00.c
PARAMETER C_USE_FPU = 0
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_NUMBER_OF_PC_BRK = 2
PARAMETER C_USE_ICACHE = 1
PARAMETER C_CACHE_BYTE_SIZE = 16384
PARAMETER C_USE_DCACHE = 1
PARAMETER C_DCACHE_BYTE_SIZE = 16384
PARAMETER C_ICACHE_BASEADDR = 0x24000000
PARAMETER C_ICACHE_HIGHADDR = 0x27ffffff
PARAMETER C_DCACHE_BASEADDR = 0x24000000
PARAMETER C_DCACHE_HIGHADDR = 0x27ffffff
PARAMETER C_USE_BARREL = 1
PARAMETER C_USE_DIV = 1
PARAMETER C_FSL_LINKS = 1
PARAMETER C_PVR = 2
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DOPB = mb_opb
BUS_INTERFACE IOPB = mb_opb
BUS_INTERFACE IXCL = ixcl
BUS_INTERFACE DXCL = dxcl
BUS_INTERFACE SFSL0 = download_link
PORT DBG_CAPTURE = DBG_CAPTURE_s
PORT DBG_CLK = DBG_CLK_s
PORT DBG_REG_EN = DBG_REG_EN_s
PORT DBG_TDI = DBG_TDI_s
PORT DBG_TDO = DBG_TDO_s
PORT DBG_UPDATE = DBG_UPDATE_s
PORT Interrupt = Interrupt
END
BEGIN opb_v20
PARAMETER INSTANCE = mb_opb
PARAMETER HW_VER = 1.10.c
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT OPB_Clk = sys_clk_s
END
BEGIN opb_mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 2.01.a
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER C_UART_WIDTH = 8
PARAMETER C_BASEADDR = 0x41400000
PARAMETER C_HIGHADDR = 0x4140ffff
PARAMETER C_WRITE_FSL_PORTS = 1
BUS_INTERFACE SOPB = mb_opb
BUS_INTERFACE MFSL0 = download_link
PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
PORT DBG_CLK_0 = DBG_CLK_s
PORT DBG_REG_EN_0 = DBG_REG_EN_s
PORT DBG_TDI_0 = DBG_TDI_s
PORT DBG_TDO_0 = DBG_TDO_s
PORT DBG_UPDATE_0 = DBG_UPDATE_s
END
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END
BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END
BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END
BEGIN opb_uartlite
PARAMETER INSTANCE = RS232
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 115200
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_CLK_FREQ = 100000000
PARAMETER C_BASEADDR = 0x40600000
PARAMETER C_HIGHADDR = 0x4060ffff
BUS_INTERFACE SOPB = mb_opb
PORT Interrupt = RS232_Interrupt
PORT RX = fpga_0_RS232_RX
PORT TX = fpga_0_RS232_TX
END
BEGIN opb_ethernet
PARAMETER INSTANCE = Ethernet_MAC
PARAMETER HW_VER = 1.04.a
PARAMETER C_DMA_PRESENT = 3
PARAMETER C_IPIF_RDFIFO_DEPTH = 32768
PARAMETER C_IPIF_WRFIFO_DEPTH = 32768
PARAMETER C_OPB_CLK_PERIOD_PS = 10000
PARAMETER C_BASEADDR = 0x40c00000
PARAMETER C_HIGHADDR = 0x40c0ffff
BUS_INTERFACE MSOPB = mb_opb
PORT IP2INTC_Irpt = Ethernet_MAC_IP2INTC_Irpt
PORT PHY_tx_er = fpga_0_Ethernet_MAC_PHY_tx_er
PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk
PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk
PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs
PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv
PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data
PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col
PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er
PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en
PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data
PORT PHY_Mii_clk = fpga_0_Ethernet_MAC_PHY_Mii_clk
PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n
PORT PHY_Mii_data = fpga_0_Ethernet_MAC_PHY_Mii_data
END
BEGIN opb_gpio
PARAMETER INSTANCE = LEDs_4Bit
PARAMETER HW_VER = 3.01.b
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_IS_DUAL = 0
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_IS_BIDIR = 0
PARAMETER C_BASEADDR = 0x40000000
PARAMETER C_HIGHADDR = 0x4000ffff
BUS_INTERFACE SOPB = mb_opb
PORT GPIO_d_out = fpga_0_LEDs_4Bit_GPIO_d_out
END
BEGIN mch_opb_ddr
PARAMETER INSTANCE = DDR_SDRAM_32Mx16
PARAMETER HW_VER = 1.00.c
PARAMETER C_INCLUDE_OPB_BURST_SUPPORT = 0
PARAMETER C_MCH_OPB_CLK_PERIOD_PS = 10000
PARAMETER C_REG_DIMM = 0
PARAMETER C_DDR_TMRD = 15000
PARAMETER C_DDR_TWR = 15000
PARAMETER C_DDR_TWTR = 1
PARAMETER C_DDR_TRAS = 40000
PARAMETER C_DDR_TRC = 65000
PARAMETER C_DDR_TRFC = 75000
PARAMETER C_DDR_TRCD = 20000
PARAMETER C_DDR_TRRD = 15000
PARAMETER C_DDR_TRP = 20000
PARAMETER C_DDR_TREFI = 7800000
PARAMETER C_DDR_DWIDTH = 16
PARAMETER C_DDR_AWIDTH = 13
PARAMETER C_DDR_COL_AWIDTH = 10
PARAMETER C_DDR_BANK_AWIDTH = 2
PARAMETER C_MEM0_BASEADDR = 0x24000000
PARAMETER C_MEM0_HIGHADDR = 0x27ffffff
BUS_INTERFACE SOPB = mb_opb
BUS_INTERFACE MCH0 = ixcl
BUS_INTERFACE MCH1 = dxcl
PORT DDR_Clk = fpga_0_DDR_SDRAM_32Mx16_DDR_Clk
PORT DDR_Clkn = fpga_0_DDR_SDRAM_32Mx16_DDR_Clkn
PORT DDR_Addr = fpga_0_DDR_SDRAM_32Mx16_DDR_Addr
PORT DDR_BankAddr = fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr
PORT DDR_CASn = fpga_0_DDR_SDRAM_32Mx16_DDR_CASn
PORT DDR_CKE = fpga_0_DDR_SDRAM_32Mx16_DDR_CKE
PORT DDR_CSn = fpga_0_DDR_SDRAM_32Mx16_DDR_CSn
PORT DDR_RASn = fpga_0_DDR_SDRAM_32Mx16_DDR_RASn
PORT DDR_WEn = fpga_0_DDR_SDRAM_32Mx16_DDR_WEn
PORT DDR_DM = fpga_0_DDR_SDRAM_32Mx16_DDR_DM
PORT DDR_DQS = fpga_0_DDR_SDRAM_32Mx16_DDR_DQS
PORT DDR_DQ = fpga_0_DDR_SDRAM_32Mx16_DDR_DQ
PORT Device_Clk90_in = clk_90_s
PORT Device_Clk90_in_n = clk_90_n_s
PORT Device_Clk = sys_clk_s
PORT Device_Clk_n = sys_clk_n_s
PORT DDR_Clk90_in = ddr_clk_90_s
PORT DDR_Clk90_in_n = ddr_clk_90_n_s
END
BEGIN opb_timer
PARAMETER INSTANCE = opb_timer_1
PARAMETER HW_VER = 1.00.b
PARAMETER C_COUNT_WIDTH = 32
PARAMETER C_ONE_TIMER_ONLY = 1
PARAMETER C_BASEADDR = 0x41c00000
PARAMETER C_HIGHADDR = 0x41c0ffff
BUS_INTERFACE SOPB = mb_opb
PORT Interrupt = opb_timer_1_Interrupt
END
BEGIN opb_intc
PARAMETER INSTANCE = opb_intc_0
PARAMETER HW_VER = 1.00.c
PARAMETER C_BASEADDR = 0x41200000
PARAMETER C_HIGHADDR = 0x4120ffff
BUS_INTERFACE SOPB = mb_opb
PORT Irq = Interrupt
PORT Intr = RS232_Interrupt & Ethernet_MAC_IP2INTC_Irpt & opb_timer_1_Interrupt
END
BEGIN util_vector_logic
PARAMETER INSTANCE = sysclk_inv
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE = 1
PARAMETER C_OPERATION = not
PORT Op1 = sys_clk_s
PORT Res = sys_clk_n_s
END
BEGIN util_vector_logic
PARAMETER INSTANCE = clk90_inv
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE = 1
PARAMETER C_OPERATION = not
PORT Op1 = clk_90_s
PORT Res = clk_90_n_s
END
BEGIN util_vector_logic
PARAMETER INSTANCE = ddr_clk90_inv
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE = 1
PARAMETER C_OPERATION = not
PORT Op1 = ddr_clk_90_s
PORT Res = ddr_clk_90_n_s
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLK90_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_DLL_FREQUENCY_MODE = LOW
PARAMETER C_EXT_RESET_HIGH = 1
PORT CLKIN = dcm_clk_s
PORT CLK0 = sys_clk_s
PORT CLK90 = clk_90_s
PORT CLKFB = sys_clk_s
PORT RST = net_gnd
PORT LOCKED = dcm_0_lock
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLK90_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_DLL_FREQUENCY_MODE = LOW
PARAMETER C_EXT_RESET_HIGH = 0
PORT CLKIN = ddr_feedback_s
PORT CLK90 = ddr_clk_90_s
PORT CLK0 = dcm_1_FB
PORT CLKFB = dcm_1_FB
PORT RST = dcm_0_lock
PORT LOCKED = dcm_1_lock
END
BEGIN fsl_v20
PARAMETER INSTANCE = download_link
PARAMETER HW_VER = 2.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT FSL_Clk = sys_clk_s
PORT SYS_Rst = sys_rst_s
END