[microblaze-uclinux] Trouble installing uClinux on XUPV2P running microblaze

[Ashish Darbari <ashish@xxxxxxxxxxxxxxx>]

Hi Friends,

I've been trying to get uClinux to install on MicroBlaze running on 
Digilent's Virtex II Pro Dev System.
In the past 2 weeks have tried using quite a few tutorials, including 
Xilinx App Notes
(www.xilinx.com/bvdocs/appnotes/*xapp730*.pdf), John Williams "uClinux 
Ready MicroBlaze" tutorial and
Digilent's own Quick Start distro 
(http://www.digilentinc.com/Data/Products/XUPV2P/uclinux-xupv2p_rev_1_1.zip).

In each of these am able to compile the hardware (upload and download) 
and compile uClinux as well. However when the
moment of truth comes --- when I download the image.bin file and do a 
con, I get no response. If I
stop the processor and get a dump of different registers, I see the 
values of many including the pc
change from 0x00000000, different at different time depending on  when I 
issue the stop command.

I'm using EDK 8.1 to build the hardware and compile uClinux under
linux running in Vmware. I suspect it may be my DDR RAM or its controller,
but am not sure if its definitely the case. In the beginning of last 
week it was mainly that I had not set up
the timer and the interrupt controller properly which I did later.

I was trying to get another project going without any external RAM, just 
use the block RAM, but don't
know if I can get uClinux to run without external RAM. Besides what is 
going to be the value for
PARAMETER main_memory in system.mss file if I'm not using DDR RAM.

I've included my system.mhs, and .mss files together with 
auto-config.in. If anyone can give me a clue
it would be very helpful, I've had a very frustrating last two weeks.

Thanks
Ashish




# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 8.1 Build EDK_I.18.7
# Fri Mar 23 13:10:14 2007
# Target Board:  Xilinx XUP Virtex-II Pro Development System Rev C
# Family:	 virtex2p
# Device:	 xc2vp30
# Package:	 ff896
# Speed Grade:	 -7
# Processor: Microblaze
# System clock frequency: 100.000000 MHz
# Debug interface: On-Chip HW Debug Module
# Data Cache: 16 KB
# Instruction Cache: 16 KB
# On Chip Memory :   8 KB
# Total Off Chip Memory : 256 MB
# - DDR_SDRAM_32Mx64 Single Rank = 256 MB
# ##############################################################################


 PARAMETER VERSION = 2.1.0


 PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = I
 PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = O
 PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = O, VEC = [6:0]
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = IO, VEC = [15:0]
 PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O
 PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O
 PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I
 PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = IO, VEC = [0:3]
 PORT fpga_0_DIPSWs_4Bit_GPIO_IO_pin = fpga_0_DIPSWs_4Bit_GPIO_IO, DIR = IO, VEC = [0:3]
 PORT fpga_0_PushButtons_5Bit_GPIO_IO_pin = fpga_0_PushButtons_5Bit_GPIO_IO, DIR = IO, VEC = [0:4]
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk, DIR = O, VEC = [0:2]
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn, DIR = O, VEC = [0:2]
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr, DIR = O, VEC = [0:12]
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr, DIR = O, VEC = [0:1]
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn, DIR = O
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn, DIR = O
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn, DIR = O
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM, DIR = O, VEC = [0:7]
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS, DIR = IO, VEC = [0:7]
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ, DIR = IO, VEC = [0:63]
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE, DIR = O
 PORT fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn, DIR = O
 PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = I, SIGIS = DCMCLK
 PORT fpga_0_DDR_CLK_FB_OUT = ddr_clk_feedback_out_s, DIR = O
 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = DCMCLK
 PORT sys_rst_pin = sys_rst_s, DIR = I


BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 4.00.a
 PARAMETER C_USE_FPU = 0
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_NUMBER_OF_PC_BRK = 2
 PARAMETER C_USE_ICACHE = 1
 PARAMETER C_CACHE_BYTE_SIZE = 16384
 PARAMETER C_USE_DCACHE = 1
 PARAMETER C_DCACHE_BYTE_SIZE = 16384
 PARAMETER C_ICACHE_BASEADDR = 0x30000000
 PARAMETER C_ICACHE_HIGHADDR = 0x3fffffff
 PARAMETER C_DCACHE_BASEADDR = 0x30000000
 PARAMETER C_DCACHE_HIGHADDR = 0x3fffffff
 PARAMETER C_ICACHE_USE_FSL = 1
 PARAMETER C_DCACHE_USE_FSL = 1
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DOPB = mb_opb
 BUS_INTERFACE IOPB = mb_opb
 PORT CLK = sys_clk_s
 PORT DBG_CAPTURE = DBG_CAPTURE_s
 PORT DBG_CLK = DBG_CLK_s
 PORT DBG_REG_EN = DBG_REG_EN_s
 PORT DBG_TDI = DBG_TDI_s
 PORT DBG_TDO = DBG_TDO_s
 PORT DBG_UPDATE = DBG_UPDATE_s
 PORT Interrupt = Interrupt
END

BEGIN opb_v20
 PARAMETER INSTANCE = mb_opb
 PARAMETER HW_VER = 1.10.c
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT OPB_Clk = sys_clk_s
END

BEGIN opb_mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER C_UART_WIDTH = 8
 PARAMETER C_BASEADDR = 0x41400000
 PARAMETER C_HIGHADDR = 0x4140ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
 PORT DBG_CLK_0 = DBG_CLK_s
 PORT DBG_REG_EN_0 = DBG_REG_EN_s
 PORT DBG_TDI_0 = DBG_TDI_s
 PORT DBG_TDO_0 = DBG_TDO_s
 PORT DBG_UPDATE_0 = DBG_UPDATE_s
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END

BEGIN opb_uartlite
 PARAMETER INSTANCE = RS232_Uart_1
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BAUDRATE = 115200
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_ODD_PARITY = 0
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_CLK_FREQ = 100000000
 PARAMETER C_BASEADDR = 0x40600000
 PARAMETER C_HIGHADDR = 0x4060ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT Interrupt = RS232_Uart_1_Interrupt
 PORT RX = fpga_0_RS232_Uart_1_RX
 PORT TX = fpga_0_RS232_Uart_1_TX
END

BEGIN opb_sysace
 PARAMETER INSTANCE = SysACE_CompactFlash
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_MEM_WIDTH = 16
 PARAMETER C_BASEADDR = 0x41800000
 PARAMETER C_HIGHADDR = 0x4180ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT SysACE_IRQ = SysACE_CompactFlash_SysACE_IRQ
 PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK
 PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA
 PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD
 PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN
 PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN
 PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN
 PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
END

BEGIN opb_gpio
 PARAMETER INSTANCE = LEDs_4Bit
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_INTERRUPT_PRESENT = 1
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 0
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_BASEADDR = 0x40000000
 PARAMETER C_HIGHADDR = 0x4000ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT IP2INTC_Irpt = LEDs_4Bit_IP2INTC_Irpt
 PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO
END

BEGIN opb_gpio
 PARAMETER INSTANCE = DIPSWs_4Bit
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 1
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_BASEADDR = 0x40020000
 PARAMETER C_HIGHADDR = 0x4002ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT GPIO_IO = fpga_0_DIPSWs_4Bit_GPIO_IO
END

BEGIN opb_gpio
 PARAMETER INSTANCE = PushButtons_5Bit
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_GPIO_WIDTH = 5
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 1
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_BASEADDR = 0x40040000
 PARAMETER C_HIGHADDR = 0x4004ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT GPIO_IO = fpga_0_PushButtons_5Bit_GPIO_IO
END

BEGIN opb_ddr
 PARAMETER INSTANCE = DDR_256MB_32MX64_rank1_row13_col10_cl2_5
 PARAMETER HW_VER = 2.00.b
 PARAMETER C_OPB_CLK_PERIOD_PS = 10000
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_NUM_CLK_PAIRS = 4
 PARAMETER C_REG_DIMM = 0
 PARAMETER C_DDR_TMRD = 20000
 PARAMETER C_DDR_TWR = 20000
 PARAMETER C_DDR_TRAS = 60000
 PARAMETER C_DDR_TRC = 90000
 PARAMETER C_DDR_TRFC = 100000
 PARAMETER C_DDR_TRCD = 30000
 PARAMETER C_DDR_TRRD = 20000
 PARAMETER C_DDR_TRP = 30000
 PARAMETER C_DDR_TREFC = 70300000
 PARAMETER C_DDR_AWIDTH = 13
 PARAMETER C_DDR_COL_AWIDTH = 10
 PARAMETER C_DDR_BANK_AWIDTH = 2
 PARAMETER C_DDR_DWIDTH = 64
 PARAMETER C_MEM0_BASEADDR = 0x30000000
 PARAMETER C_MEM0_HIGHADDR = 0x3fffffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT DDR_Addr = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr
 PORT DDR_BankAddr = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr
 PORT DDR_CASn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn
 PORT DDR_CKE = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE
 PORT DDR_CSn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn
 PORT DDR_RASn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn
 PORT DDR_WEn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn
 PORT DDR_DM = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM
 PORT DDR_DQS = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS
 PORT DDR_DQ = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ
 PORT DDR_Clk = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk & ddr_clk_feedback_out_s
 PORT DDR_Clkn = fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn & 0b0
 PORT Device_Clk90_in = clk_90_s
 PORT Device_Clk90_in_n = clk_90_n_s
 PORT Device_Clk = sys_clk_s
 PORT Device_Clk_n = sys_clk_n_s
 PORT DDR_Clk90_in = ddr_clk_90_s
 PORT DDR_Clk90_in_n = ddr_clk_90_n_s
END

BEGIN opb_timer
 PARAMETER INSTANCE = opb_timer_1
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_COUNT_WIDTH = 32
 PARAMETER C_ONE_TIMER_ONLY = 1
 PARAMETER C_BASEADDR = 0x41c00000
 PARAMETER C_HIGHADDR = 0x41c0ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT Interrupt = opb_timer_1_Interrupt
END

BEGIN opb_intc
 PARAMETER INSTANCE = opb_intc_0
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_BASEADDR = 0x41200000
 PARAMETER C_HIGHADDR = 0x4120ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT Irq = Interrupt
 PORT Intr = RS232_Uart_1_Interrupt & SysACE_CompactFlash_SysACE_IRQ & LEDs_4Bit_IP2INTC_Irpt & opb_timer_1_Interrupt
END

BEGIN util_vector_logic
 PARAMETER INSTANCE = sysclk_inv
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE = 1
 PARAMETER C_OPERATION = not
 PORT Op1 = sys_clk_s
 PORT Res = sys_clk_n_s
END

BEGIN util_vector_logic
 PARAMETER INSTANCE = clk90_inv
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE = 1
 PARAMETER C_OPERATION = not
 PORT Op1 = clk_90_s
 PORT Res = clk_90_n_s
END

BEGIN util_vector_logic
 PARAMETER INSTANCE = ddr_clk90_inv
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE = 1
 PARAMETER C_OPERATION = not
 PORT Op1 = ddr_clk_90_s
 PORT Res = ddr_clk_90_n_s
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLK90_BUF = TRUE
 PARAMETER C_CLKIN_PERIOD = 10.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_DLL_FREQUENCY_MODE = LOW
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT CLKIN = dcm_clk_s
 PORT CLK0 = sys_clk_s
 PORT CLK90 = clk_90_s
 PORT CLKFB = sys_clk_s
 PORT RST = net_gnd
 PORT LOCKED = dcm_0_lock
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLK90_BUF = TRUE
 PARAMETER C_CLKIN_PERIOD = 10.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_DLL_FREQUENCY_MODE = LOW
 PARAMETER C_PHASE_SHIFT = 60
 PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT CLKIN = ddr_feedback_s
 PORT CLK90 = ddr_clk_90_s
 PORT CLK0 = dcm_1_FB
 PORT CLKFB = dcm_1_FB
 PORT RST = dcm_0_lock
 PORT LOCKED = dcm_1_lock
END

 PARAMETER VERSION = 2.2.0


BEGIN OS
 PARAMETER OS_NAME = uclinux
 PARAMETER OS_VER = 1.00.d
 PARAMETER PROC_INSTANCE = microblaze_0
 PARAMETER lmb_memory = dlmb_cntlr
 PARAMETER flash_memory_bank = 0
 PARAMETER main_memory_bank = 0
 PARAMETER main_memory = DDR_256MB_32MX64_rank1_row13_col10_cl2_5
 PARAMETER TARGET_DIR = L:/MyProjectFiles/ucLinuxReadyMicroBlaze
END


BEGIN PROCESSOR
 PARAMETER DRIVER_NAME = cpu
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = microblaze_0
 PARAMETER COMPILER = mb-gcc
 PARAMETER ARCHIVER = mb-ar
 PARAMETER XMDSTUB_PERIPHERAL = debug_module
END


BEGIN DRIVER
 PARAMETER DRIVER_NAME = opbarb
 PARAMETER DRIVER_VER = 1.02.a
 PARAMETER HW_INSTANCE = mb_opb
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = uartlite
 PARAMETER DRIVER_VER = 1.00.b
 PARAMETER HW_INSTANCE = debug_module
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = bram
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = dlmb_cntlr
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = bram
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = ilmb_cntlr
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = uartlite
 PARAMETER DRIVER_VER = 1.00.b
 PARAMETER HW_INSTANCE = RS232_Uart_1
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = sysace
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = SysACE_CompactFlash
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = gpio
 PARAMETER DRIVER_VER = 2.00.a
 PARAMETER HW_INSTANCE = LEDs_4Bit
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = gpio
 PARAMETER DRIVER_VER = 2.00.a
 PARAMETER HW_INSTANCE = DIPSWs_4Bit
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = gpio
 PARAMETER DRIVER_VER = 2.00.a
 PARAMETER HW_INSTANCE = PushButtons_5Bit
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = ddr
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = DDR_256MB_32MX64_rank1_row13_col10_cl2_5
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = tmrctr
 PARAMETER DRIVER_VER = 1.00.b
 PARAMETER HW_INSTANCE = opb_timer_1
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = intc
 PARAMETER DRIVER_VER = 1.00.c
 PARAMETER HW_INSTANCE = opb_intc_0
END


############################################################
# 
# CAUTION: This file is automatically generated by libgen.
# Version: Xilinx EDK 8.1 EDK_I.18.7 
# Description: uClinux Configuration File
# 
############################################################



# MAIN_MEMORY Settings
define_hex CONFIG_XILINX_ERAM_START 0x30000000
define_hex CONFIG_XILINX_ERAM_SIZE 0x10000000

# LMB_MEMORY Settings
define_hex CONFIG_XILINX_LMB_START 0x00000000
define_hex CONFIG_XILINX_LMB_SIZE 0x00002000

# System Clock Frequency
define_int CONFIG_XILINX_CPU_CLOCK_FREQ 100000000

# Definitions for MICROBLAZE0
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
define_string CONFIG_XILINX_MICROBLAZE0_FAMILY virtex2p
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
define_int CONFIG_XILINX_MICROBLAZE0_D_OPB 1
define_int CONFIG_XILINX_MICROBLAZE0_D_LMB 1
define_int CONFIG_XILINX_MICROBLAZE0_I_OPB 1
define_int CONFIG_XILINX_MICROBLAZE0_I_LMB 1
define_int CONFIG_XILINX_MICROBLAZE0_USE_BARREL 0
define_int CONFIG_XILINX_MICROBLAZE0_USE_DIV 0
define_int CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL 1
define_int CONFIG_XILINX_MICROBLAZE0_USE_FPU 0
define_int CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR 0
define_int CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR 0
define_int CONFIG_XILINX_MICROBLAZE0_UNALIGNED_EXCEPTIONS 0
define_int CONFIG_XILINX_MICROBLAZE0_ILL_OPCODE_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_IOPB_BUS_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DOPB_BUS_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DIV_ZERO_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_FPU_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DEBUG_ENABLED 1
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_PBRK 2
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_RD_ADDR_BRK 0
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_WR_ADDR_BRK 0
define_int CONFIG_XILINX_MICROBLAZE0_INTERRUPT_IS_EDGE 0
define_int CONFIG_XILINX_MICROBLAZE0_EDGE_IS_POSITIVE 1
define_int CONFIG_XILINX_MICROBLAZE0_FSL_LINKS 0
define_int CONFIG_XILINX_MICROBLAZE0_FSL_DATA_SIZE 32
define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_BASEADDR 0x30000000
define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_HIGHADDR 0x3FFFFFFF
define_int CONFIG_XILINX_MICROBLAZE0_USE_ICACHE 1
define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_ICACHE_WR 1
define_int CONFIG_XILINX_MICROBLAZE0_ADDR_TAG_BITS 14
define_int CONFIG_XILINX_MICROBLAZE0_CACHE_BYTE_SIZE 16384
define_int CONFIG_XILINX_MICROBLAZE0_ICACHE_USE_FSL 1
define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_BASEADDR 0x30000000
define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_HIGHADDR 0x3FFFFFFF
define_int CONFIG_XILINX_MICROBLAZE0_USE_DCACHE 1
define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_DCACHE_WR 1
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_ADDR_TAG 14
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_BYTE_SIZE 16384
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_USE_FSL 1
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
define_string CONFIG_XILINX_MICROBLAZE0_HW_VER 4.00.a

# Definitions for LMB_BRAM_IF_CNTLR_0
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE dlmb_cntlr
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_BASEADDR 0x00000000
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HIGHADDR 0x00001FFF
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_MASK 0x50000000
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_AWIDTH 32
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_DWIDTH 32
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE dlmb_cntlr
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HW_VER 1.00.b

# Definitions for LMB_BRAM_IF_CNTLR_1
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE ilmb_cntlr
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_BASEADDR 0x00000000
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HIGHADDR 0x00001FFF
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_MASK 0x50000000
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_AWIDTH 32
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_DWIDTH 32
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE ilmb_cntlr
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HW_VER 1.00.b

# Definitions for V20_0
define_string CONFIG_XILINX_V20_0_INSTANCE mb_opb
define_hex CONFIG_XILINX_V20_0_BASEADDR 0xFFFFFFFF
define_hex CONFIG_XILINX_V20_0_HIGHADDR 0x00000000
define_int CONFIG_XILINX_V20_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_V20_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_V20_0_NUM_MASTERS 2
define_int CONFIG_XILINX_V20_0_NUM_SLAVES 9
define_int CONFIG_XILINX_V20_0_USE_LUT_OR 1
define_int CONFIG_XILINX_V20_0_EXT_RESET_HIGH 0
define_int CONFIG_XILINX_V20_0_DYNAM_PRIORITY 0
define_int CONFIG_XILINX_V20_0_PARK 0
define_int CONFIG_XILINX_V20_0_PROINTRFCE 0
define_int CONFIG_XILINX_V20_0_REG_GRANTS 1
define_int CONFIG_XILINX_V20_0_DEV_BLK_ID 0
define_int CONFIG_XILINX_V20_0_DEV_MIR_ENABLE 0
define_string CONFIG_XILINX_V20_0_INSTANCE mb_opb
define_string CONFIG_XILINX_V20_0_HW_VER 1.10.c

# Definitions for MDM_0
define_string CONFIG_XILINX_MDM_0_INSTANCE debug_module
define_hex CONFIG_XILINX_MDM_0_BASEADDR 0x41400000
define_hex CONFIG_XILINX_MDM_0_HIGHADDR 0x4140FFFF
define_int CONFIG_XILINX_MDM_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_MDM_0_OPB_AWIDTH 32
define_string CONFIG_XILINX_MDM_0_FAMILY virtex2p
define_int CONFIG_XILINX_MDM_0_MB_DBG_PORTS 1
define_int CONFIG_XILINX_MDM_0_USE_UART 1
define_int CONFIG_XILINX_MDM_0_UART_WIDTH 8
define_int CONFIG_XILINX_MDM_0_WRITE_FSL_PORTS 0
define_string CONFIG_XILINX_MDM_0_INSTANCE debug_module
define_string CONFIG_XILINX_MDM_0_HW_VER 2.00.a

# Definitions for UARTLITE_0
define_string CONFIG_XILINX_UARTLITE_0_INSTANCE RS232_Uart_1
define_hex CONFIG_XILINX_UARTLITE_0_BASEADDR 0x40600000
define_hex CONFIG_XILINX_UARTLITE_0_HIGHADDR 0x4060FFFF
define_int CONFIG_XILINX_UARTLITE_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_UARTLITE_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_UARTLITE_0_DATA_BITS 8
define_int CONFIG_XILINX_UARTLITE_0_CLK_FREQ 100000000
define_int CONFIG_XILINX_UARTLITE_0_BAUDRATE 115200
define_int CONFIG_XILINX_UARTLITE_0_USE_PARITY 0
define_int CONFIG_XILINX_UARTLITE_0_ODD_PARITY 0
define_string CONFIG_XILINX_UARTLITE_0_INSTANCE RS232_Uart_1
define_string CONFIG_XILINX_UARTLITE_0_HW_VER 1.00.b
define_int CONFIG_XILINX_UARTLITE_0_IRQ 3

# Definitions for SYSACE_0
define_string CONFIG_XILINX_SYSACE_0_INSTANCE SysACE_CompactFlash
define_hex CONFIG_XILINX_SYSACE_0_BASEADDR 0x41800000
define_hex CONFIG_XILINX_SYSACE_0_HIGHADDR 0x4180FFFF
define_int CONFIG_XILINX_SYSACE_0_MEM_WIDTH 16
define_int CONFIG_XILINX_SYSACE_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_SYSACE_0_OPB_AWIDTH 32
define_string CONFIG_XILINX_SYSACE_0_INSTANCE SysACE_CompactFlash
define_string CONFIG_XILINX_SYSACE_0_HW_VER 1.00.c
define_int CONFIG_XILINX_SYSACE_0_IRQ 2

# Definitions for GPIO_0
define_string CONFIG_XILINX_GPIO_0_INSTANCE LEDs_4Bit
define_hex CONFIG_XILINX_GPIO_0_BASEADDR 0x40000000
define_hex CONFIG_XILINX_GPIO_0_HIGHADDR 0x4000FFFF
define_int CONFIG_XILINX_GPIO_0_USER_ID_CODE 3
define_int CONFIG_XILINX_GPIO_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_GPIO_0_OPB_DWIDTH 32
define_string CONFIG_XILINX_GPIO_0_FAMILY virtex2p
define_int CONFIG_XILINX_GPIO_0_GPIO_WIDTH 4
define_int CONFIG_XILINX_GPIO_0_ALL_INPUTS 0
define_int CONFIG_XILINX_GPIO_0_INTERRUPT_PRESENT 1
define_int CONFIG_XILINX_GPIO_0_IS_BIDIR 0
define_hex CONFIG_XILINX_GPIO_0_DOUT_DEFAULT 0x00000000
define_hex CONFIG_XILINX_GPIO_0_TRI_DEFAULT 0xFFFFFFFF
define_int CONFIG_XILINX_GPIO_0_IS_DUAL 0
define_int CONFIG_XILINX_GPIO_0_ALL_INPUTS_2 0
define_int CONFIG_XILINX_GPIO_0_IS_BIDIR_2 1
define_hex CONFIG_XILINX_GPIO_0_DOUT_DEFAULT_2 0x00000000
define_hex CONFIG_XILINX_GPIO_0_TRI_DEFAULT_2 0xFFFFFFFF
define_string CONFIG_XILINX_GPIO_0_INSTANCE LEDs_4Bit
define_string CONFIG_XILINX_GPIO_0_HW_VER 3.01.b
define_int CONFIG_XILINX_GPIO_0_IRQ 1

# Definitions for GPIO_1
define_string CONFIG_XILINX_GPIO_1_INSTANCE DIPSWs_4Bit
define_hex CONFIG_XILINX_GPIO_1_BASEADDR 0x40020000
define_hex CONFIG_XILINX_GPIO_1_HIGHADDR 0x4002FFFF
define_int CONFIG_XILINX_GPIO_1_USER_ID_CODE 3
define_int CONFIG_XILINX_GPIO_1_OPB_AWIDTH 32
define_int CONFIG_XILINX_GPIO_1_OPB_DWIDTH 32
define_string CONFIG_XILINX_GPIO_1_FAMILY virtex2p
define_int CONFIG_XILINX_GPIO_1_GPIO_WIDTH 4
define_int CONFIG_XILINX_GPIO_1_ALL_INPUTS 1
define_int CONFIG_XILINX_GPIO_1_INTERRUPT_PRESENT 0
define_int CONFIG_XILINX_GPIO_1_IS_BIDIR 1
define_hex CONFIG_XILINX_GPIO_1_DOUT_DEFAULT 0x00000000
define_hex CONFIG_XILINX_GPIO_1_TRI_DEFAULT 0xFFFFFFFF
define_int CONFIG_XILINX_GPIO_1_IS_DUAL 0
define_int CONFIG_XILINX_GPIO_1_ALL_INPUTS_2 0
define_int CONFIG_XILINX_GPIO_1_IS_BIDIR_2 1
define_hex CONFIG_XILINX_GPIO_1_DOUT_DEFAULT_2 0x00000000
define_hex CONFIG_XILINX_GPIO_1_TRI_DEFAULT_2 0xFFFFFFFF
define_string CONFIG_XILINX_GPIO_1_INSTANCE DIPSWs_4Bit
define_string CONFIG_XILINX_GPIO_1_HW_VER 3.01.b

# Definitions for GPIO_2
define_string CONFIG_XILINX_GPIO_2_INSTANCE PushButtons_5Bit
define_hex CONFIG_XILINX_GPIO_2_BASEADDR 0x40040000
define_hex CONFIG_XILINX_GPIO_2_HIGHADDR 0x4004FFFF
define_int CONFIG_XILINX_GPIO_2_USER_ID_CODE 3
define_int CONFIG_XILINX_GPIO_2_OPB_AWIDTH 32
define_int CONFIG_XILINX_GPIO_2_OPB_DWIDTH 32
define_string CONFIG_XILINX_GPIO_2_FAMILY virtex2p
define_int CONFIG_XILINX_GPIO_2_GPIO_WIDTH 5
define_int CONFIG_XILINX_GPIO_2_ALL_INPUTS 1
define_int CONFIG_XILINX_GPIO_2_INTERRUPT_PRESENT 0
define_int CONFIG_XILINX_GPIO_2_IS_BIDIR 1
define_hex CONFIG_XILINX_GPIO_2_DOUT_DEFAULT 0x00000000
define_hex CONFIG_XILINX_GPIO_2_TRI_DEFAULT 0xFFFFFFFF
define_int CONFIG_XILINX_GPIO_2_IS_DUAL 0
define_int CONFIG_XILINX_GPIO_2_ALL_INPUTS_2 0
define_int CONFIG_XILINX_GPIO_2_IS_BIDIR_2 1
define_hex CONFIG_XILINX_GPIO_2_DOUT_DEFAULT_2 0x00000000
define_hex CONFIG_XILINX_GPIO_2_TRI_DEFAULT_2 0xFFFFFFFF
define_string CONFIG_XILINX_GPIO_2_INSTANCE PushButtons_5Bit
define_string CONFIG_XILINX_GPIO_2_HW_VER 3.01.b

# Definitions for DDR_0
define_string CONFIG_XILINX_DDR_0_INSTANCE DDR_256MB_32MX64_rank1_row13_col10_cl2_5
define_int CONFIG_XILINX_DDR_0_DDR_ASYNSUPPORT 0
define_int CONFIG_XILINX_DDR_0_INCLUDE_BURST_SUPPORT 0
define_int CONFIG_XILINX_DDR_0_REG_DIMM 0
define_int CONFIG_XILINX_DDR_0_EXTRA_TSU 0
define_int CONFIG_XILINX_DDR_0_NUM_BANKS_MEM 1
define_int CONFIG_XILINX_DDR_0_NUM_CLK_PAIRS 4
define_string CONFIG_XILINX_DDR_0_FAMILY virtex2p
define_int CONFIG_XILINX_DDR_0_DDR_TMRD 20000
define_int CONFIG_XILINX_DDR_0_DDR_TWR 20000
define_int CONFIG_XILINX_DDR_0_DDR_TWTR 1
define_int CONFIG_XILINX_DDR_0_DDR_TRAS 60000
define_int CONFIG_XILINX_DDR_0_DDR_TRC 90000
define_int CONFIG_XILINX_DDR_0_DDR_TRFC 100000
define_int CONFIG_XILINX_DDR_0_DDR_TRCD 30000
define_int CONFIG_XILINX_DDR_0_DDR_TRRD 20000
define_int CONFIG_XILINX_DDR_0_DDR_TREFC 70300000
define_int CONFIG_XILINX_DDR_0_DDR_TREFI 7800000
define_int CONFIG_XILINX_DDR_0_DDR_TRP 30000
define_int CONFIG_XILINX_DDR_0_DDR_CAS_LAT 2
define_int CONFIG_XILINX_DDR_0_DDR_DWIDTH 64
define_int CONFIG_XILINX_DDR_0_DDR_AWIDTH 13
define_int CONFIG_XILINX_DDR_0_DDR_COL_AWIDTH 10
define_int CONFIG_XILINX_DDR_0_DDR_BANK_AWIDTH 2
define_hex CONFIG_XILINX_DDR_0_MEM0_BASEADDR 0x30000000
define_hex CONFIG_XILINX_DDR_0_MEM0_HIGHADDR 0x3FFFFFFF
define_hex CONFIG_XILINX_DDR_0_MEM1_BASEADDR 0xFFFFFFFF
define_hex CONFIG_XILINX_DDR_0_MEM1_HIGHADDR 0x00000000
define_hex CONFIG_XILINX_DDR_0_MEM2_BASEADDR 0xFFFFFFFF
define_hex CONFIG_XILINX_DDR_0_MEM2_HIGHADDR 0x00000000
define_hex CONFIG_XILINX_DDR_0_MEM3_BASEADDR 0xFFFFFFFF
define_hex CONFIG_XILINX_DDR_0_MEM3_HIGHADDR 0x00000000
define_int CONFIG_XILINX_DDR_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_DDR_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_DDR_0_OPB_CLK_PERIOD_PS 10000
define_int CONFIG_XILINX_DDR_0_SIM_INIT_TIME_PS 200000000
define_string CONFIG_XILINX_DDR_0_INSTANCE DDR_256MB_32MX64_rank1_row13_col10_cl2_5
define_string CONFIG_XILINX_DDR_0_HW_VER 2.00.b

# Definitions for TIMER_0
define_string CONFIG_XILINX_TIMER_0_INSTANCE opb_timer_1
define_string CONFIG_XILINX_TIMER_0_FAMILY virtex2p
define_int CONFIG_XILINX_TIMER_0_COUNT_WIDTH 32
define_int CONFIG_XILINX_TIMER_0_ONE_TIMER_ONLY 1
define_int CONFIG_XILINX_TIMER_0_TRIG0_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_TRIG1_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_GEN0_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_GEN1_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_TIMER_0_OPB_DWIDTH 32
define_hex CONFIG_XILINX_TIMER_0_BASEADDR 0x41C00000
define_hex CONFIG_XILINX_TIMER_0_HIGHADDR 0x41C0FFFF
define_string CONFIG_XILINX_TIMER_0_INSTANCE opb_timer_1
define_string CONFIG_XILINX_TIMER_0_HW_VER 1.00.b
define_int CONFIG_XILINX_TIMER_0_IRQ 0

# Definitions for INTC_0
define_string CONFIG_XILINX_INTC_0_INSTANCE opb_intc_0
define_string CONFIG_XILINX_INTC_0_FAMILY virtex2p
define_int CONFIG_XILINX_INTC_0_Y 0
define_int CONFIG_XILINX_INTC_0_X 0
define_string CONFIG_XILINX_INTC_0_U_SET intc
define_int CONFIG_XILINX_INTC_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_INTC_0_OPB_DWIDTH 32
define_hex CONFIG_XILINX_INTC_0_BASEADDR 0x41200000
define_hex CONFIG_XILINX_INTC_0_HIGHADDR 0x4120FFFF
define_int CONFIG_XILINX_INTC_0_NUM_INTR_INPUTS 4
define_hex CONFIG_XILINX_INTC_0_KIND_OF_INTR 0x00000008
define_hex CONFIG_XILINX_INTC_0_KIND_OF_EDGE 0x00000008
define_hex CONFIG_XILINX_INTC_0_KIND_OF_LVL 0x00000007
define_int CONFIG_XILINX_INTC_0_HAS_IPR 1
define_int CONFIG_XILINX_INTC_0_HAS_SIE 1
define_int CONFIG_XILINX_INTC_0_HAS_CIE 1
define_int CONFIG_XILINX_INTC_0_HAS_IVR 1
define_int CONFIG_XILINX_INTC_0_IRQ_IS_LEVEL 1
define_int CONFIG_XILINX_INTC_0_IRQ_ACTIVE 1
define_string CONFIG_XILINX_INTC_0_INSTANCE opb_intc_0
define_string CONFIG_XILINX_INTC_0_HW_VER 1.00.c

# Peripheral counts
define_int CONFIG_XILINX_SYSACE_NUM_INSTANCES 1
define_int CONFIG_XILINX_V20_NUM_INSTANCES 1
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_NUM_INSTANCES 2
define_int CONFIG_XILINX_TIMER_NUM_INSTANCES 1
define_int CONFIG_XILINX_INTC_NUM_INSTANCES 1
define_int CONFIG_XILINX_DDR_NUM_INSTANCES 1
define_int CONFIG_XILINX_UARTLITE_NUM_INSTANCES 1
define_int CONFIG_XILINX_MDM_NUM_INSTANCES 1
define_int CONFIG_XILINX_GPIO_NUM_INSTANCES 3