Re: [microblaze-uclinux] How to add customer peripheral with IP core to

On 4/25/07, Kris Chaplin <kris.chaplin@xxxxxxxxxx > wrote:

Hello William

Apologies, I am not a Verilog user, so it took me a few moments to spot this.

I think that XST is complaining as it cannot enumerate the ports of the fft component. I guess when you had the project in ISE, the coregen module was also in the project.

Please try adding the following to your verilog, at the very bottom of the file, after endmodule:

// empty module for port direction information

module fft (

sclr, fwd_inv_we, rfd, start, fwd_inv, dv, unload, scale_sch_we, done, clk, busy, edone, ovflo, scale_sch, xn_re, xk_im, xn_index, xk_re, xn_im,

xk_index

);

input sclr;

input fwd_inv_we;

output rfd;

input start;

input fwd_inv;

output dv;

input unload;

input scale_sch_we;

output done;

input clk;

output busy;

output edone;

output ovflo;

input [7 : 0] scale_sch;

input [15 : 0] xn_re;

output [15 : 0] xk_im;

output [7 : 0] xn_index;

output [15 : 0] xk_re;

input [15 : 0] xn_im;

output [7 : 0] xk_index;

endmodule

This seems to get around the problem, and XST reports in the .srp file for the peripheral:

WARNING:Xst:2211 - "C:\backup\customer\zhang\AEC\pcores\coproc_v1_00_a/hdl/verilog/user_logic.v" line 534: Instantiating black box module <fft>.

So all looks good J

Please let me know if this implements for you ok (I don't have EDK 8.1 installed, and so was trying this out on 8.2 )

Best regards

Kris

--
----------------------------------------------------------------------------

/ /\/ Kris Chaplin
\ \   Senior Applications Engineer - Embedded Processors
/ /   Xilinx Europe
\_\/\ +44 (0)1932-836563

From: William Zhang [mailto: espzzh@xxxxxxxxx]
Sent: 25 April 2007 08:35
To: Kris Chaplin

Subject: Re: [microblaze-uclinux] How to add customer peripheral with IP core to EDK

Hi Kris,

Thanks for your kindness to help. I attached the whole project tree which I rebuilded it from scratch. The peripheral was also rebuilt and
stored in my local resposiories. And I imported it to the XPS project with the option of HDL, Netlist option which create/modify the bbd
and mdf file and copy the ngc file. You can check it under pcores\coproc_v1_00_a.

Change the attached file name to project.zip. GMail apparenently scan the zip file and won;t allow me to send the attachement.

Thanks a lot!

Regards,
William

On 4/24/07, Kris Chaplin < kris.chaplin@xxxxxxxxxx> wrote:

Feel free to buzz the file over, and I can take a quick look.

Best regards

Kris

--
----------------------------------------------------------------------------

/ /\/ Kris Chaplin
\ \   Senior Applications Engineer - Embedded Processors
/ /   Xilinx Europe
\_\/\ +44 (0)1932-836563

From: owner- microblaze-uclinux@xxxxxxxxxxxxxx [mailto:owner- microblaze-uclinux@xxxxxxxxxxxxxx] On Behalf Of William Zhang
Sent: 24 April 2007 18:34
To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: Re: [microblaze-uclinux] How to add customer peripheral with IP core to EDK

Yes, I did... The Import Peripheral Wizard with netlist option did exactly same thing, but it fails too.

There must be something I am missing here in my environment.

On 4/24/07, Kris Chaplin < kris.chaplin@xxxxxxxxxx> wrote:

Hello William,

Have you specified the fft core in the bbd file for the peripheral?

Eg:

files

fft.ngc

Also does the mpd file for the peripheral have the line " OPTION STYLE = mix"?

Best regards

Kris Chaplin

--
----------------------------------------------------------------------------

/ /\/ Kris Chaplin
\ \   Senior Applications Engineer - Embedded Processors
/ /   Xilinx Europe
\_\/\ +44 (0)1932-836563

From: owner-microblaze-uclinux@xxxxxxxxxxxxxx [mailto:owner-microblaze-uclinux@xxxxxxxxxxxxxx ] On Behalf Of William Zhang
Sent: 24 April 2007 10:21
To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: [microblaze-uclinux] How to add customer peripheral with IP core to EDK

Hi All,

I am trying to add a customized OPB peripheral to the Microblaze
system in EDK/Platform Studio 8.1. My peripheral uses a FFT core
generated from Core Generator so it only comes with ngc netlist.

I instantiate the core in the user_logic.v. And I was able to
synthesize the peripheral using generated ISE project file by adding
the IP source file (core wizard) to the project. But when I add
peripheral to the system and generate the netlist, the XST tool always
complains: ERROR:HDLCompilers:87 - "D:\TechDrive\Project\Xilinx

\AEC\pcores\coproc_v1_00_a/hdl/verilog/user_logic.v" line 536 Could not
find module/primitive 'fft'

I did quite a bit search in the help,manual of EDK document,Core
Generator, XPS help but I could not find any for such case.
Luckly I was able to find some help from the fpga-faq forum. One of them
suggests to add a bbd file and change mpd file in the core's
resposiories data folder. I tried exactly same step but it does not
work for me. I also tried to import the the peripheral to design
through both XST prj file and PAO file but neither of them helps.

After spending two nights on this "intergration" issue without any
luck, I am pretty upset about the Xilinx tool chain especially the
document part! I thought this is very typical case(EDK->Peripheral-
>LogiCore) and there should be some sort of help easy for acess for
newbie. Maybe I am too blind to find it. But if somebody can point me
out where the document is or workaround it through some tricky way,
I'll greatly appreciate it!

Thanks a lot!
William