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Re: [microblaze-uclinux] Spartan3E board and u-boot question

To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: Re: [microblaze-uclinux] Spartan3E board and u-boot question
From: "Stephane Rousseau" <stephaner@xxxxxxxxx>
Date: Wed, 9 May 2007 14:30:06 -0400
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Thank you Leonid for your answer. I verified the setup and CONFIGs seems ok.

I begin to suspect someting with the DDR SDRAM IP for the Spartan3E Board.
I've recreated a small system and used the memorytest application, the
memory test fails.

- Entering main() --
Starting MemoryTest for DDR_SDRAM_32Mx16:
 Running 32-bit test...FAILED!
 Running 16-bit test...FAILED!
 Running 8-bit test...FAILED!
-- Exiting main() --

I've these warnings in the EDK build part:

Xilinx Platform Studio (XPS)
Xilinx EDK 8.1.02 Build EDK_I.20.4
....
WARNING:NgdBuild:6 - Ignoring pad-related IOBDELAY property on non-pad net
  "fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_O<0>".
WARNING:NgdBuild:6 - Ignoring pad-related IOBDELAY property on non-pad net
  "fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_O<1>".
WARNING:NgdBuild:6 - Ignoring pad-related IOBDELAY property on non-pad net
  "fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_T<0>".
WARNING:NgdBuild:6 - Ignoring pad-related IOBDELAY property on non-pad net
  "fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_T<1>".
WARNING:NgdBuild:6 - Ignoring pad-related IOBDELAY property on non-pad net
  "fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_O<0>".
...

WARNING:NgdBuild:440 - FF primitive
  'ddr_sdram_32mx16/ddr_sdram_32mx16/DDR_CTRL_I/RDDATA_PATH_I/ddr_sdram_32mx16_
  wrapper_V2_ASYNCH_FIFO_I/BU11' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
  'ddr_sdram_32mx16/ddr_sdram_32mx16/DDR_CTRL_I/RDDATA_PATH_I/ddr_sdram_32mx16_
  wrapper_V2_ASYNCH_FIFO_I/BU16' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
  'ddr_sdram_32mx16/ddr_sdram_32mx16/DDR_CTRL_I/RDDATA_PATH_I/ddr_sdram_32mx16_
  wrapper_V2_ASYNCH_FIFO_I/BU21' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
  'ddr_sdram_32mx16/ddr_sdram_32mx16/DDR_CTRL_I/RDDATA_PATH_I/ddr_sdram_32mx16_
  wrapper_V2_ASYNCH_FIFO_I/BU26' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
  'ddr_sdram_32mx16/ddr_sdram_32mx16/DDR_CTRL_I/RDDATA_PATH_I/ddr_sdram_32mx16_
  wrapper_V2_ASYNCH_FIFO_I/BU31' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
  'ddr_sdram_32mx16/ddr_sdram_32mx16/DDR_CTRL_I/RDDATA_PATH_I/ddr_sdram_32mx16_
  wrapper_V2_ASYNCH_FIFO_I/BU36' has unconnected output pin
...
WARNING:Route:447 - CLK Net:dlmb_port_BRAM_Clk may have excessive skew because
  1220 CLK pins failed to route using a CLK template.
WARNING:Route:447 - CLK Net:ddr_dev_clk_s may have excessive skew because
  144 CLK pins failed to route using a CLK template.
WARNING:Route:447 - CLK Net:DBG_CLK_s may have excessive skew because
  112 CLK pins failed to route using a CLK template.
WARNING:Route:447 - CLK Net:ddr_clk_90_s may have excessive skew because
  77 CLK pins failed to route using a CLK template.
WARNING:Route:447 - CLK Net:ddr_dev_clk_90_s may have excessive skew because
  10 CLK pins failed to route using a CLK template.
...
WARNING:Timing:3233 - Timing Constraint
  "TS_dcm_0_dcm_0_CLK2X_BUF = PERIOD TIMEGRP "dcm_0_dcm_0_CLK2X_BUF"
          TS_sys_clk_pin / 2 HIGH 50%;"
   fails the minimum period check for the input clock ddr_dev_clk_s to DCM
  dcm_1/dcm_1/DCM_INST because the period constraint value (10000 ps) is less
  than the minimum internal period limit of 11110 ps.   Please increase the
  period of the constraint to remove this timing failure.
WARNING:Timing:3235 - Timing Constraint
  "TS_dcm_0_dcm_0_CLK2X_BUF = PERIOD TIMEGRP "dcm_0_dcm_0_CLK2X_BUF"
          TS_sys_clk_pin / 2 HIGH 50%;"
   fails the minimum period check for the output clock dcm_1/dcm_1/CLK90_BUF
  from DCM dcm_1/dcm_1/DCM_INST because the period constraint value (10000 ps)
  is less than the minimum internal period limit of 11110 ps.   Please increase
  the period of the constraint to remove this timing failure.
WARNING:Timing:3235 - Timing Constraint
  "TS_dcm_0_dcm_0_CLK2X_BUF = PERIOD TIMEGRP "dcm_0_dcm_0_CLK2X_BUF"
          TS_sys_clk_pin / 2 HIGH 50%;"
   fails the minimum period check for the output clock dcm_1/dcm_1/CLK0_BUF
  from DCM dcm_1/dcm_1/DCM_INST because the period constraint value (10000 ps)
  is less than the minimum internal period limit of 11110 ps.   Please increase
  the period of the constraint to remove this timing failure.




So, I restarted with the Xilinx-Spartan3E500-RevC-edk81 from the
petalinux0.01rc1 release.

I've rebuilt the Xilinx-Spartan3E500-RevC-edk81 on EDK8.1.02 and
FS-BOOT still hang.



=================================================
FS-BOOT First Stage Bootloader (c) 2006 PetaLogix
=================================================
FS-BOOT: System initialisation completed.
FS-BOOT: No existing image in FLASH.  Starting image download.
FS-BOOT: Waiting for SREC image....
FS-BOOT: Image download successful.
FS-BOOT: Warning image location differ from default boot location. Image will no
t boot automatically after POR.
FS-BOOT: Press 'n' to boot old image.
FS-BOOT: Use new image.
FS-BOOT: Booting image...

And I have warnings in EDK too :

Xilinx Platform Studio (XPS)
Xilinx EDK 8.1.02 Build EDK_I.20.4
...
WARNING:MDT - dcm_2_lock (LOCKED) -
  C:\Tempo\proj-p1-Xilinx-Spartan3E500-RevC-edk81\system.mhs line 438 -
  floating connection!
...
ARNING:NgdBuild:6 - Ignoring pad-related IOBDELAY property on non-pad net
  "fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_O<0>".
WARNING:NgdBuild:6 - Ignoring pad-related IOBDELAY property on non-pad net
  "fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_O<1>".
WARNING:NgdBuild:6 - Ignoring pad-related IOBDELAY property on non-pad net
  "fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_T<0>".
WARNING:NgdBuild:6 - Ignoring pad-related IOBDELAY property on non-pad net
  "fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_T<1>".
WARNING:NgdBuild:6 - Ignoring pad-related IOBDELAY property on non-pad net
...
WARNING:NgdBuild:440 - FF primitive
  'ddr_sdram_16mx16/ddr_sdram_16mx16/DDR_CTRL_I/RDDATA_PATH_I/ddr_sdram_16mx16_
  wrapper_V2_ASYNCH_FIFO_I/ddr_sdram_16mx16_wrapper_async_fifo_v4_0/mem/distmem
  /dist_mem/DPRAM/DPRAM0/DPRAM0REG_SP/REG' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
  'ddr_sdram_16mx16/ddr_sdram_16mx16/DDR_CTRL_I/RDDATA_PATH_I/ddr_sdram_16mx16_
  wrapper_V2_ASYNCH_FIFO_I/ddr_sdram_16mx16_wrapper_async_fifo_v4_0/mem/distmem
  /dist_mem/DPRAM/DPRAM0/DPRAM1REG_SP/REG' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
  'ddr_sdram_16mx16/ddr_sdram_16mx16/DDR_CTRL_I/RDDATA_PATH_I/ddr_sdram_16mx16_
  wrapper_V2_ASYNCH_FIFO_I/ddr_sdram_16mx16_wrapper_async_fifo_v4_0/mem/distmem
  /dist_mem/DPRAM/DPRAM0/DPRAM2REG_SP/REG' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
  'ddr_sdram_16mx16/ddr_sdram_16mx16/DDR_CTRL_I/RDDATA_PATH_I/ddr_sdram_16mx16_
  wrapper_V2_ASYNCH_FIFO_I/ddr_sdram_16mx16_wrapper_async_fifo_v4_0/mem/distmem
  /dist_mem/DPRAM/DPRAM0/DPRAM3REG_SP/REG' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
  'ddr_sdram_16mx16/ddr_sdram_16mx16/DDR_CTRL_I/RDDATA_PATH_I/ddr_sdram_16mx16_
  wrapper_V2_ASYNCH_FIFO_I/ddr_sdram_16mx16_wrapper_async_fifo_v4_0/mem/distmem
  /dist_mem/DPRAM/DPRAM0/DPRAM4REG_SP/REG' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
...
WARNING:NgdBuild:443 - SFF primitive
  'ddr_sdram_16mx16/ddr_sdram_16mx16/DDR_CTRL_I/CNTRS_I/XSR_CNT_I/CARRY_OUT_I'
  has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
  'ddr_sdram_16mx16/ddr_sdram_16mx16/DDR_CTRL_I/CNTRS_I/RCCNT_I/CARRY_OUT_I'
  has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
  'ddr_sdram_16mx16/ddr_sdram_16mx16/DDR_CTRL_I/CNTRS_I/RFCCNT_I/CARRY_OUT_I'
  has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
  'ddr_sdram_16mx16/ddr_sdram_16mx16/DDR_CTRL_I/CNTRS_I/RASCNT_I/CARRY_OUT_I'
  has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
  'ddr_sdram_16mx16/ddr_sdram_16mx16/MCH_OPB_IPIF_I/CH_I0/RD_BUF_I/READDATA_FIF
  O/I_ADDR_CNTR/I_UP_DWN_COUNTER/I_CARRY_OUT' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
  'ddr_sdram_16mx16/ddr_sdram_16mx16/MCH_OPB_IPIF_I/CH_I0/ACCESS_BUF_I/ACCESS_F
  IFO/I_ADDR_CNTR/I_UP_DWN_COUNTER/I_CARRY_OUT' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
  'ddr_sdram_16mx16/ddr_sdram_16mx16/MCH_OPB_IPIF_I/CH_I1/RD_BUF_I/READDATA_FIF
  O/I_ADDR_CNTR/I_UP_DWN_COUNTER/I_CARRY_OUT' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
...
WARNING:NgdBuild:483 - Attribute "IOBDELAY" on
  "fpga_0_DDR_SDRAM_16Mx16_DDR_DQ_O<7>" is on the wrong type of object.  Please
  see the Constraints Guide for more information on this attribute.
WARNING:NgdBuild:483 - Attribute "IOBDELAY" on
  "fpga_0_DDR_SDRAM_16Mx16_DDR_DQ_O<8>" is on the wrong type of object.  Please
  see the Constraints Guide for more information on this attribute.
WARNING:NgdBuild:483 - Attribute "IOBDELAY" on
  "fpga_0_DDR_SDRAM_16Mx16_DDR_DQ_O<9>" is on the wrong type of object.  Please
  see the Constraints Guide for more information on this attribute.
WARNING:NgdBuild:483 - Attribute "IOBDELAY" on
  "fpga_0_DDR_SDRAM_16Mx16_DDR_DQ_O<10>" is on the wrong type of object.
  Please see the Constraints Guide for more information on this attribute.
WARNING:NgdBuild:483 - Attribute "IOBDELAY" on
  "fpga_0_DDR_SDRAM_16Mx16_DDR_DQ_O<11>" is on the wrong type of object.
  Please see the Constraints Guide for more information on this attribute.
WARNING:NgdBuild:483 - Attribute "IOBDELAY" on
  "fpga_0_DDR_SDRAM_16Mx16_DDR_DQ_O<12>" is on the wrong type of object.
  Please see the Constraints Guide for more information on this attribute.
WARNING:NgdBuild:483 - Attribute "IOBDELAY" on
  "fpga_0_DDR_SDRAM_16Mx16_DDR_DQ_O<13>" is on the wrong type of object.
  Please see the Constraints Guide for more information on this attribute.
WARNING:NgdBuild:483 - Attribute "IOBDELAY" on
  "fpga_0_DDR_SDRAM_16Mx16_DDR_DQ_O<14>" is on the wrong type of object.
  Please see the Constraints Guide for more information on this attribute.
WARNING:NgdBuild:483 - Attribute "IOBDELAY" on
  "fpga_0_DDR_SDRAM_16Mx16_DDR_DQ_O<15>" is on the wrong type of object.
  Please see the Constraints Guide for more information on this attribute.
WARNING:NgdBuild:483 - Attribute "IOBDELAY" on
  "fpga_0_DDR_SDRAM_16Mx16_DDR_DQ_T<0>" is on the wrong type of object.  Please
  see the Constraints Guide for more information on this attribute.
WARNING:NgdBuild:483 - Attribute "IOBDELAY" on
  "fpga_0_DDR_SDRAM_16Mx16_DDR_DQ_T<1>" is on the wrong type of object.  Please
  see the Constraints Guide for more information on this attribute.
WARNING:NgdBuild:483 - Attribute "IOBDELAY" on
  "fpga_0_DDR_SDRAM_16Mx16_DDR_DQ_T<2>" is on the wrong type of object.  Please
  see the Constraints Guide for more information on this attribute.
...
WARNING:Timing:3233 - Timing Constraint
  "TS_dcm_0_dcm_0_CLK2X_BUF = PERIOD TIMEGRP "dcm_0_dcm_0_CLK2X_BUF"
          TS_sys_clk_pin / 2 HIGH 50%;"
   fails the minimum period check for the input clock ddr_dev_clk_s
to DCM dcm_1/dcm_1/DCM_INST because the period
  constraint value (10000 ps) is less than the minimum internal
period limit of 11110 ps.   Please increase the period
  of the constraint to remove this timing failure.
WARNING:Timing:3235 - Timing Constraint
  "TS_dcm_0_dcm_0_CLK2X_BUF = PERIOD TIMEGRP "dcm_0_dcm_0_CLK2X_BUF"
          TS_sys_clk_pin / 2 HIGH 50%;"
   fails the minimum period check for the output clock
dcm_1/dcm_1/CLK90_BUF from DCM dcm_1/dcm_1/DCM_INST because the
  period constraint value (10000 ps) is less than the minimum
internal period limit of 11110 ps.   Please increase the
  period of the constraint to remove this timing failure.
WARNING:Timing:3235 - Timing Constraint
  "TS_dcm_0_dcm_0_CLK2X_BUF = PERIOD TIMEGRP "dcm_0_dcm_0_CLK2X_BUF"
          TS_sys_clk_pin / 2 HIGH 50%;"
   fails the minimum period check for the output clock
dcm_1/dcm_1/CLK0_BUF from DCM dcm_1/dcm_1/DCM_INST because the
  period constraint value (10000 ps) is less than the minimum
internal period limit of 11110 ps.   Please increase the
  period of the constraint to remove this timing failure.
...
Analyzing file fs-boot/executable.elf...
INFO:MDT - BRAM lmb_bram will be initialized with ELF of processor microblaze_0
Running Data2Mem with the following command:
data2mem -bm implementation/system_bd -bt implementation/system.bit  -bd
fs-boot/executable.elf tag lmb_bram  -o b implementation/download.bit

Memory Initialization completed successfully.
Done!


Then I upload the already build demo for the Spartan3e-500 board from
Petalogix using boot-onetime.sh,
the following output appear:

Nothing appears after succesfull transfer.

Then I've tried to upload a pre-built reference design
Xilinx-Spartan3E500-RevC from the petalinux distribution.

==========================================
FS-BOOT First Stage Bootloader (c) 2006 PetaLogix
=================================================
FS-BOOT: System initialisation completed.
FS-BOOT: No existing image in FLASH.  Starting image download.
FS-BOOT: Waiting for SREC image....
-- Entering main() --
Starting MemoryTest for DDR_SDRAM_32Mx16:
 Running 32-bit test...


Now, I suspect my DDR RAM is dead.

Does anyone get the warnings about the DDRRAM on their builts?

Thank you,

Stephane Rousseau

On 5/4/07, Leonid <Leonid@xxxxxxxxx> wrote:

Your srec file looks OK, u-boot will be downloaded to address
0x23fc0000. Thee can be many reasons why you don't see any output. One
of them is that u-boot's serial default baudrate is different from that
of fs-boot or you didn't import EDK compilation parameters to software
properly and clock and/or UART offset is different (check autoconf.h
file).

Leonid.

-----Original Message-----
From: owner-microblaze-uclinux@xxxxxxxxxxxxxx
[mailto:owner-microblaze-uclinux@xxxxxxxxxxxxxx] On Behalf Of Stephane
Rousseau
Sent: Friday, May 04, 2007 12:20 PM
To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: [microblaze-uclinux] Spartan3E board and u-boot question

Hi everyone,

Now, i'm able to build the hardware and compile for the Spartan3e-500
board.

I send the bit fit to the board,
see the FS-BOOT,
send the u-boot.srec file and see the running cursor

The following messages appear:

FS-BOOT: Warning image location differ from default boot location.
Image will not boot automatically after POR.

FS-BOOT: Press 'n' to boot old image.

FS-BOOT: Use new image.

FS-BOOT: Booting image...


I'm trying to figure the problem, is it the SDRAM, the u-boot
configuration problem?

The variable CONFIG_XILINK_ERAM_START is 0x22000000

And here are the two first lines of the u-boot.srec:

S00E0000752D626F6F742E73726563C0
S31523FC00009400C001B00023F6202000002021FFFC31

Does anyone had the same problem or an idea?

Thank you,

Stephane Rousseau
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Follow-Ups:
- RE: [microblaze-uclinux] Spartan3E board and u-boot question
  - From: Leonid

References:
- [microblaze-uclinux] Spartan3E board and u-boot question
  - From: Stephane Rousseau
- RE: [microblaze-uclinux] Spartan3E board and u-boot question
  - From: Leonid

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