[microblaze-uclinux] uCLinux cannot allocate EMAClite interrupt

[Jean-Yves Ouellet <jouellet7@xxxxxxxxxxxx>]

I run XPS 8.1.02i on a Windows PC and the Petalinux tools on a Linux PC. 
Samba is used to transfer auto-config.in and image.bin between the two 
PCs. To download image.bin to the target (Spartan-3E Starter Kit Rev-D), 
I run microblaze_0_bootloop and then issue the commands "dow" and "con" 
in XMD.

I can compile and boot uCLinux (without networking support) on 
MicroBlaze without Flash and EMAClite. However, if I add networking 
support to uCLinux and EMAClite to MicroBlaze, I get the following error:

Linux version 2.4.32-uc0 (jouellet@jy-compaq) (gcc version 3.4.1 ( 
Xilinx EDK 
8.                                                                                

1.01 Build EDK_I.19.4 080506 )) #8 Thu May 17 17:28:39 EDT 
2007                                                              
On node 0 totalpages: 8192                         
zone(0): 8192 pages.                   
zone(1): 0 pages.                
zone(2): 0 pages.                
CPU: MICROBLAZE              
Kernel command line: ¸                     
Console: xmbserial on UARTLite                             
Calibrating delay loop... 24.67 
BogoMIPS                                       
Memory: 32MB = 32MB total                        
Memory: 30256KB available (1038K code, 1113K data, 48K 
init)                                                           
Dentry cache hash table entries: 4096 (order: 3, 32768 
bytes)                                                            
Inode cache hash table entries: 2048 (order: 2, 16384 
bytes)                                                           
Mount cache hash table entries: 512 (order: 0, 
409                                               
Buffer cache hash table entries: 1024 (order: 0, 4096 
bytes)                                                           
Page-cache hash table entries: 8192 (order: 3, 32768 
bytes)                                                          
POSIX conformance testing by UNIFIX                                  
Linux NET4.0 for Linux 2.4                         
Based upon Swansea University Computer Society 
NET3.039                                                      
Initializing RT netlink socket                             
Microblaze UARTlite serial driver version 
1.00                                             
ttyS0 at 0x40600000 (irq = 2) is a Microblaze 
UARTlite                         
Starting kswapd
RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
eth0: using fifo mode.
eth0: No PHY detected.  Assuming a PHY at address 0.
eth0: Xilinx EMACLite #0 at 0x40E00000 mapped to 0x40E00000, irq=2
uclinux[mtd]: RAM probe address=0x22141ed0 size=0xd8000
uclinux[mtd]: root filesystem index=0
NET4: Linux TCP/IP 1.0 for NET4.0
IP Protocols: ICMP, UDP, TCP
IP: routing cache hash table of 512 buckets, 4Kbytes
TCP: Hash tables configured (established 2048 bind 4096)
NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
VFS: Mounted root (cramfs filesystem) readonly.
Freeing init memory: 48K
Mounting proc:
Mounting var:
Populating /var:
Running local start scripts.
Mounting /etc/config:
Populating /etc/config:
flatfsd: Nonexistent or bad flatfs (-48), creating new one...
flatfeth0: Could not allocate interrupt 2.
sd: Failed to write flatfs


It looks like interrupt 2 cannot be allocated to EMAClite because it is 
already allocated to UARTlite. But according to auto-config.in (see the 
attached file), interrupt 3 (instead of interrupt 2) should be allocated 
to UARTlite.

Any idea?

J-Y

############################################################
# 
# CAUTION: This file is automatically generated by libgen.
# EDK Version: Xilinx EDK 8.1.02 EDK_I.20.4 
# Description: PetaLinux Configuration File
# 
############################################################


# MAIN_MEMORY Settings
define_hex CONFIG_XILINX_ERAM_START 0x22000000
define_hex CONFIG_XILINX_ERAM_SIZE 0x02000000

# LMB_MEMORY Settings
define_hex CONFIG_XILINX_LMB_START 0x00000000
define_hex CONFIG_XILINX_LMB_SIZE 0x00002000

# System Clock Frequency
define_int CONFIG_XILINX_CPU_CLOCK_FREQ 50000000

# Definitions for MICROBLAZE0
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
define_string CONFIG_XILINX_MICROBLAZE0_FAMILY spartan3e
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
define_int CONFIG_XILINX_MICROBLAZE0_D_OPB 1
define_int CONFIG_XILINX_MICROBLAZE0_D_LMB 1
define_int CONFIG_XILINX_MICROBLAZE0_I_OPB 1
define_int CONFIG_XILINX_MICROBLAZE0_I_LMB 1
define_int CONFIG_XILINX_MICROBLAZE0_USE_BARREL 0
define_int CONFIG_XILINX_MICROBLAZE0_USE_DIV 0
define_int CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL 1
define_int CONFIG_XILINX_MICROBLAZE0_USE_FPU 0
define_int CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR 0
define_int CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR 0
define_int CONFIG_XILINX_MICROBLAZE0_UNALIGNED_EXCEPTIONS 0
define_int CONFIG_XILINX_MICROBLAZE0_ILL_OPCODE_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_IOPB_BUS_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DOPB_BUS_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DIV_ZERO_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_FPU_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DEBUG_ENABLED 1
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_PC_BRK 2
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_RD_ADDR_BRK 0
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_WR_ADDR_BRK 0
define_int CONFIG_XILINX_MICROBLAZE0_INTERRUPT_IS_EDGE 0
define_int CONFIG_XILINX_MICROBLAZE0_EDGE_IS_POSITIVE 1
define_int CONFIG_XILINX_MICROBLAZE0_FSL_LINKS 0
define_int CONFIG_XILINX_MICROBLAZE0_FSL_DATA_SIZE 32
define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_BASEADDR 0x22000000
define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_HIGHADDR 0x23FFFFFF
define_int CONFIG_XILINX_MICROBLAZE0_USE_ICACHE 1
define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_ICACHE_WR 1
define_int CONFIG_XILINX_MICROBLAZE0_ADDR_TAG_BITS 14
define_int CONFIG_XILINX_MICROBLAZE0_CACHE_BYTE_SIZE 2048
define_int CONFIG_XILINX_MICROBLAZE0_ICACHE_USE_FSL 1
define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_BASEADDR 0x22000000
define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_HIGHADDR 0x23FFFFFF
define_int CONFIG_XILINX_MICROBLAZE0_USE_DCACHE 1
define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_DCACHE_WR 1
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_ADDR_TAG 12
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_BYTE_SIZE 8192
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_USE_FSL 1
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
define_string CONFIG_XILINX_MICROBLAZE0_HW_VER 4.00.a

# Definitions for LMB_BRAM_IF_CNTLR_0
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE dlmb_cntlr
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_BASEADDR 0x00000000
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HIGHADDR 0x00001FFF
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_MASK 0x02600000
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_AWIDTH 32
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_DWIDTH 32
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE dlmb_cntlr
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HW_VER 1.00.b

# Definitions for LMB_BRAM_IF_CNTLR_1
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE ilmb_cntlr
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_BASEADDR 0x00000000
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HIGHADDR 0x00001FFF
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_MASK 0x02600000
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_AWIDTH 32
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_DWIDTH 32
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE ilmb_cntlr
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HW_VER 1.00.b

# Definitions for V20_0
define_string CONFIG_XILINX_V20_0_INSTANCE mb_opb
define_hex CONFIG_XILINX_V20_0_BASEADDR 0xFFFFFFFF
define_hex CONFIG_XILINX_V20_0_HIGHADDR 0x00000000
define_int CONFIG_XILINX_V20_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_V20_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_V20_0_NUM_MASTERS 2
define_int CONFIG_XILINX_V20_0_NUM_SLAVES 6
define_int CONFIG_XILINX_V20_0_USE_LUT_OR 1
define_int CONFIG_XILINX_V20_0_EXT_RESET_HIGH 1
define_int CONFIG_XILINX_V20_0_DYNAM_PRIORITY 0
define_int CONFIG_XILINX_V20_0_PARK 0
define_int CONFIG_XILINX_V20_0_PROC_INTRFCE 0
define_int CONFIG_XILINX_V20_0_REG_GRANTS 1
define_int CONFIG_XILINX_V20_0_DEV_BLK_ID 0
define_int CONFIG_XILINX_V20_0_DEV_MIR_ENABLE 0
define_string CONFIG_XILINX_V20_0_INSTANCE mb_opb
define_string CONFIG_XILINX_V20_0_HW_VER 1.10.c

# Definitions for MDM_0
define_string CONFIG_XILINX_MDM_0_INSTANCE debug_module
define_hex CONFIG_XILINX_MDM_0_BASEADDR 0x41400000
define_hex CONFIG_XILINX_MDM_0_HIGHADDR 0x4140FFFF
define_int CONFIG_XILINX_MDM_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_MDM_0_OPB_AWIDTH 32
define_string CONFIG_XILINX_MDM_0_FAMILY spartan3e
define_int CONFIG_XILINX_MDM_0_MB_DBG_PORTS 1
define_int CONFIG_XILINX_MDM_0_USE_UART 0
define_int CONFIG_XILINX_MDM_0_UART_WIDTH 8
define_int CONFIG_XILINX_MDM_0_WRITE_FSL_PORTS 0
define_string CONFIG_XILINX_MDM_0_INSTANCE debug_module
define_string CONFIG_XILINX_MDM_0_HW_VER 2.00.a
define_int CONFIG_XILINX_MDM_0_IRQ 0

# Definitions for UARTLITE_0
define_string CONFIG_XILINX_UARTLITE_0_INSTANCE RS232_DCE
define_hex CONFIG_XILINX_UARTLITE_0_BASEADDR 0x40600000
define_hex CONFIG_XILINX_UARTLITE_0_HIGHADDR 0x4060FFFF
define_int CONFIG_XILINX_UARTLITE_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_UARTLITE_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_UARTLITE_0_DATA_BITS 8
define_int CONFIG_XILINX_UARTLITE_0_CLK_FREQ 50000000
define_int CONFIG_XILINX_UARTLITE_0_BAUDRATE 9600
define_int CONFIG_XILINX_UARTLITE_0_USE_PARITY 0
define_int CONFIG_XILINX_UARTLITE_0_ODD_PARITY 0
define_string CONFIG_XILINX_UARTLITE_0_INSTANCE RS232_DCE
define_string CONFIG_XILINX_UARTLITE_0_HW_VER 1.00.b
define_int CONFIG_XILINX_UARTLITE_0_IRQ 3

# Definitions for MCH_OPB_DDR_0
define_string CONFIG_XILINX_MCH_OPB_DDR_0_INSTANCE DDR_SDRAM_32Mx16
define_string CONFIG_XILINX_MCH_OPB_DDR_0_FAMILY spartan3e
define_int CONFIG_XILINX_MCH_OPB_DDR_0_REG_DIMM 0
define_int CONFIG_XILINX_MCH_OPB_DDR_0_NUM_BANKS_MEM 1
define_int CONFIG_XILINX_MCH_OPB_DDR_0_NUM_CLK_PAIRS 1
define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_ASYNC_SUPPORT 1
define_int CONFIG_XILINX_MCH_OPB_DDR_0_EXTRA_TSU 0
define_int CONFIG_XILINX_MCH_OPB_DDR_0_USE_OPEN_ROW_MNGT 0
define_int CONFIG_XILINX_MCH_OPB_DDR_0_INCLUDE_DDR_PIPE 1
define_int CONFIG_XILINX_MCH_OPB_DDR_0_NUM_CHANNELS 2
define_int CONFIG_XILINX_MCH_OPB_DDR_0_PRIORITY_MODE 0
define_int CONFIG_XILINX_MCH_OPB_DDR_0_INCLUDE_OPB_IPIF 1
define_int CONFIG_XILINX_MCH_OPB_DDR_0_INCLUDE_OPB_BURST_SUPPORT 0
define_int CONFIG_XILINX_MCH_OPB_DDR_0_INCLUDE_TIMEOUT_CNTR 0
define_int CONFIG_XILINX_MCH_OPB_DDR_0_TIMEOUT 16
define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH_OPB_DWIDTH 32
define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH_OPB_AWIDTH 32
define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH_OPB_CLK_PERIOD_PS 20000
define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TMRD 15000
define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TWR 15000
define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TWTR 1
define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TRAS 40000
define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TRC 65000
define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TRFC 75000
define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TRCD 20000
define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TRRD 15000
define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TREFI 7800000
define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TRP 20000
define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TXSR 80000
define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_CAS_LAT 2
define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_DWIDTH 16
define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_AWIDTH 13
define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_COL_AWIDTH 10
define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_BANK_AWIDTH 2
define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH0_PROTOCOL 0
define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH0_ACCESSBUF_DEPTH 16
define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH0_RDDATABUF_DEPTH 16
define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH1_PROTOCOL 0
define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH1_ACCESSBUF_DEPTH 16
define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH1_RDDATABUF_DEPTH 16
define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH2_PROTOCOL 0
define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH2_ACCESSBUF_DEPTH 16
define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH2_RDDATABUF_DEPTH 16
define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH3_PROTOCOL 0
define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH3_ACCESSBUF_DEPTH 16
define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH3_RDDATABUF_DEPTH 16
define_int CONFIG_XILINX_MCH_OPB_DDR_0_XCL0_LINESIZE 4
define_int CONFIG_XILINX_MCH_OPB_DDR_0_XCL0_WRITEXFER 1
define_int CONFIG_XILINX_MCH_OPB_DDR_0_XCL1_LINESIZE 4
define_int CONFIG_XILINX_MCH_OPB_DDR_0_XCL1_WRITEXFER 1
define_int CONFIG_XILINX_MCH_OPB_DDR_0_XCL2_LINESIZE 4
define_int CONFIG_XILINX_MCH_OPB_DDR_0_XCL2_WRITEXFER 1
define_int CONFIG_XILINX_MCH_OPB_DDR_0_XCL3_LINESIZE 4
define_int CONFIG_XILINX_MCH_OPB_DDR_0_XCL3_WRITEXFER 1
define_hex CONFIG_XILINX_MCH_OPB_DDR_0_MEM0_BASEADDR 0x22000000
define_hex CONFIG_XILINX_MCH_OPB_DDR_0_MEM0_HIGHADDR 0x23FFFFFF
define_hex CONFIG_XILINX_MCH_OPB_DDR_0_MEM1_BASEADDR 0xFFFFFFFF
define_hex CONFIG_XILINX_MCH_OPB_DDR_0_MEM1_HIGHADDR 0x00000000
define_hex CONFIG_XILINX_MCH_OPB_DDR_0_MEM2_BASEADDR 0xFFFFFFFF
define_hex CONFIG_XILINX_MCH_OPB_DDR_0_MEM2_HIGHADDR 0x00000000
define_hex CONFIG_XILINX_MCH_OPB_DDR_0_MEM3_BASEADDR 0xFFFFFFFF
define_hex CONFIG_XILINX_MCH_OPB_DDR_0_MEM3_HIGHADDR 0x00000000
define_int CONFIG_XILINX_MCH_OPB_DDR_0_SIM_INIT_TIME_PS 100000000
define_string CONFIG_XILINX_MCH_OPB_DDR_0_INSTANCE DDR_SDRAM_32Mx16
define_string CONFIG_XILINX_MCH_OPB_DDR_0_HW_VER 1.00.b

# Definitions for ETHERNETLITE_0
define_string CONFIG_XILINX_ETHERNETLITE_0_INSTANCE Ethernet_MAC
define_int CONFIG_XILINX_ETHERNETLITE_0_DUPLEX 1
define_int CONFIG_XILINX_ETHERNETLITE_0_RX_PING_PONG 0
define_int CONFIG_XILINX_ETHERNETLITE_0_TX_PING_PONG 0
define_hex CONFIG_XILINX_ETHERNETLITE_0_BASEADDR 0x40E00000
define_hex CONFIG_XILINX_ETHERNETLITE_0_HIGHADDR 0x40E0FFFF
define_int CONFIG_XILINX_ETHERNETLITE_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_ETHERNETLITE_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_ETHERNETLITE_0_OPB_CLK_PERIOD_PS 20000
define_string CONFIG_XILINX_ETHERNETLITE_0_FAMILY spartan3e
define_string CONFIG_XILINX_ETHERNETLITE_0_INSTANCE Ethernet_MAC
define_string CONFIG_XILINX_ETHERNETLITE_0_HW_VER 1.01.b
define_int CONFIG_XILINX_ETHERNETLITE_0_IRQ 2

# Definitions for TIMER_0
define_string CONFIG_XILINX_TIMER_0_INSTANCE opb_timer_1
define_string CONFIG_XILINX_TIMER_0_FAMILY spartan3e
define_int CONFIG_XILINX_TIMER_0_COUNT_WIDTH 32
define_int CONFIG_XILINX_TIMER_0_ONE_TIMER_ONLY 1
define_int CONFIG_XILINX_TIMER_0_TRIG0_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_TRIG1_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_GEN0_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_GEN1_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_TIMER_0_OPB_DWIDTH 32
define_hex CONFIG_XILINX_TIMER_0_BASEADDR 0x41C00000
define_hex CONFIG_XILINX_TIMER_0_HIGHADDR 0x41C0FFFF
define_string CONFIG_XILINX_TIMER_0_INSTANCE opb_timer_1
define_string CONFIG_XILINX_TIMER_0_HW_VER 1.00.b
define_int CONFIG_XILINX_TIMER_0_IRQ 1

# Definitions for INTC_0
define_string CONFIG_XILINX_INTC_0_INSTANCE opb_intc_0
define_string CONFIG_XILINX_INTC_0_FAMILY spartan3e
define_int CONFIG_XILINX_INTC_0_Y 0
define_int CONFIG_XILINX_INTC_0_X 0
define_string CONFIG_XILINX_INTC_0_U_SET intc
define_int CONFIG_XILINX_INTC_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_INTC_0_OPB_DWIDTH 32
define_hex CONFIG_XILINX_INTC_0_BASEADDR 0x41200000
define_hex CONFIG_XILINX_INTC_0_HIGHADDR 0x4120FFFF
define_int CONFIG_XILINX_INTC_0_NUM_INTR_INPUTS 4
define_hex CONFIG_XILINX_INTC_0_KIND_OF_INTR 0x0000000D
define_hex CONFIG_XILINX_INTC_0_KIND_OF_EDGE 0x0000000D
define_hex CONFIG_XILINX_INTC_0_KIND_OF_LVL 0x00000002
define_int CONFIG_XILINX_INTC_0_HAS_IPR 1
define_int CONFIG_XILINX_INTC_0_HAS_SIE 1
define_int CONFIG_XILINX_INTC_0_HAS_CIE 1
define_int CONFIG_XILINX_INTC_0_HAS_IVR 1
define_int CONFIG_XILINX_INTC_0_IRQ_IS_LEVEL 1
define_int CONFIG_XILINX_INTC_0_IRQ_ACTIVE 1
define_string CONFIG_XILINX_INTC_0_INSTANCE opb_intc_0
define_string CONFIG_XILINX_INTC_0_HW_VER 1.00.c

# Peripheral counts
define_int CONFIG_XILINX_V20_NUM_INSTANCES 1
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_NUM_INSTANCES 2
define_int CONFIG_XILINX_TIMER_NUM_INSTANCES 1
define_int CONFIG_XILINX_ETHERNETLITE_NUM_INSTANCES 1
define_int CONFIG_XILINX_MCH_OPB_DDR_NUM_INSTANCES 1
define_int CONFIG_XILINX_INTC_NUM_INSTANCES 1
define_int CONFIG_XILINX_UARTLITE_NUM_INSTANCES 1
define_int CONFIG_XILINX_MDM_NUM_INSTANCES 1