[microblaze-uclinux] Error: Could not read PHY control register

[Ryan Marotz <rmarotz@xxxxxxxxxx>]

All,

I'm trying to get a simple uClinux image running on a base Microblaze 
build.  I used the Xilinx Base System Builder wizard to create my 
project for the Avnet Virtex-4 LX Evaluation Board (LX60) v1.0.  When I 
run the memory and peripheral tests, they pass.  Next in the Software 
Platform Settings I changed the OS to uclinux v1.00.d and made the 
following changes to the configuration for OS:
lmb_memory: dlmb_cntlr
main_memory_bank: 0
main_memory: DDR_SDRAM_16Mx16
stdin: RS232
stdout: RS232
TARGET_DIR: ./linux

I created a uClinux image using the auto-config.in file that was created 
using Generate Libraries and BSPs.  When I load and run the image from 
the sdram I get the following error (full bootup capture below):
eth0: Could not read PHY control register; error 1003

I have included below the ethernet section out of the mhs file and the 
generated auto-config.in.  Thanks in advance for the help.

-Ryan

=== FULL BOOT CAPTURE
Linux version 2.4.32-uc0 (devel@localhost) (gcc version 3.4.1 ( Xilinx 
EDK 8.2 Build EDK_Im.12 180506 )) #116 Fri Mar 16 02:14:43 EDT 2007
On node 0 totalpages: 8192
zone(0): 8192 pages.
zone(1): 0 pages.
zone(2): 0 pages.
CPU: MICROBLAZE
Kernel command line: ¸
Console: xmbserial on UARTLite
Calibrating delay loop... 3.46 BogoMIPS
Memory: 32MB = 32MB total
Memory: 28892KB available (1346K code, 2167K data, 64K init)
Dentry cache hash table entries: 4096 (order: 3, 32768 bytes)
Inode cache hash table entries: 2048 (order: 2, 16384 bytes)
Mount cache hash table entries: 512 (order: 0, 4096 bytes)
Buffer cache hash table entries: 1024 (order: 0, 4096 bytes)
Page-cache hash table entries: 8192 (order: 3, 32768 bytes)
POSIX conformance testing by UNIFIX
Linux NET4.0 for Linux 2.4
Based upon Swansea University Computer Society NET3.039
Initializing RT netlink socket
Microblaze UARTlite serial driver version 1.00
ttyS0 at 0x40600000 (irq = 2) is a Microblaze UARTlite
ttyS1 at 0xffffc000 (irq = 3) is a Microblaze UARTlite
Starting kswapd
xgpio #0 at 0x40000000 mapped to 0x40000000
xgpio #1 at 0x40020000 mapped to 0x40020000
xgpio #2 at 0x40040000 mapped to 0x40040000
Xilinx GPIO registered
RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
eth0: using fifo mode.
eth0: No PHY detected.  Assuming a PHY at address 0.
eth0: Xilinx EMAC #0 at 0x40C00000 mapped to 0x40C00000, irq=1
eth0: id 2.0l; block id 11, type 1
uclinux[mtd]: RAM probe address=0x2418d1fc size=0x1e2000
uclinux[mtd]: root filesystem index=0
NET4: Linux TCP/IP 1.0 for NET4.0
IP Protocols: ICMP, UDP, TCP
IP: routing cache hash table of 512 buckets, 4Kbytes
TCP: Hash tables configured (established 2048 bind 4096)
eth0: Could not read PHY control register; error 1003
IP-Config: Incomplete network configuration information.
NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
VFS: Mounted root (romfs filesystem) readonly.
Freeing init memory: 64K
Mounting proc:
Mounting var:
Populating /var:
Running local start scripts.
Mounting /etc/config:
Populating /etc/config:
flatfsd: Nonexistent or bad flatfs (-48), creating new one...
flatfsd: Failed to write flatfs (-48): No such device
flatfsd: Created 5 configuration files (210 bytes)
Setting hostname:
Setting up interface lo:
Setting up interface eth0:
eth0: Could not read PHY control register; error 1003
eth0: Could not read PHY control register; error 1003
eth0: Terminating link monitoring.
Starting inetd:

uclinux-auto login:
=== END CAPTURE

=== ETHERNET SECTION OF MHS
BEGIN opb_ethernet
 PARAMETER INSTANCE = Ethernet_MAC
 PARAMETER HW_VER = 1.04.a
 PARAMETER C_DMA_PRESENT = 1
 PARAMETER C_IPIF_RDFIFO_DEPTH = 32768
 PARAMETER C_IPIF_WRFIFO_DEPTH = 32768
 PARAMETER C_OPB_CLK_PERIOD_PS = 10000
 PARAMETER C_BASEADDR = 0x40c00000
 PARAMETER C_HIGHADDR = 0x40c0ffff
 PARAMETER C_DEV_BLK_ID = 0
 BUS_INTERFACE SOPB = mb_opb
 PORT IP2INTC_Irpt = Ethernet_MAC_IP2INTC_Irpt
 PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk
 PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk
 PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs
 PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv
 PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data
 PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col
 PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er
 PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en
 PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data
 PORT PHY_Mii_clk = fpga_0_Ethernet_MAC_PHY_Mii_clk
 PORT PHY_Mii_data = fpga_0_Ethernet_MAC_PHY_Mii_data
END
=== END SECTION

=== auto-config.in
############################################################
#
# CAUTION: This file is automatically generated by libgen.
# Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
# Description: uClinux Configuration File
#
############################################################



# MAIN_MEMORY Settings
define_hex CONFIG_XILINX_ERAM_START 0x24000000
define_hex CONFIG_XILINX_ERAM_SIZE 0x02000000

# LMB_MEMORY Settings
define_hex CONFIG_XILINX_LMB_START 0x00000000
define_hex CONFIG_XILINX_LMB_SIZE 0x00010000

# System Clock Frequency
define_int CONFIG_XILINX_CPU_CLOCK_FREQ 100000000

# Definitions for MICROBLAZE0
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
define_string CONFIG_XILINX_MICROBLAZE0_FAMILY virtex4
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
define_int CONFIG_XILINX_MICROBLAZE0_D_OPB 1
define_int CONFIG_XILINX_MICROBLAZE0_D_LMB 1
define_int CONFIG_XILINX_MICROBLAZE0_I_OPB 1
define_int CONFIG_XILINX_MICROBLAZE0_I_LMB 1
define_int CONFIG_XILINX_MICROBLAZE0_USE_BARREL 0
define_int CONFIG_XILINX_MICROBLAZE0_USE_DIV 0
define_int CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL 1
define_int CONFIG_XILINX_MICROBLAZE0_USE_FPU 0
define_int CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR 0
define_int CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR 0
define_int CONFIG_XILINX_MICROBLAZE0_UNALIGNED_EXCEPTIONS 0
define_int CONFIG_XILINX_MICROBLAZE0_ILL_OPCODE_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_IOPB_BUS_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DOPB_BUS_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DIV_ZERO_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_FPU_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DEBUG_ENABLED 1
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_PBRK 2
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_RD_ADDR_BRK 0
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_WR_ADDR_BRK 0
define_int CONFIG_XILINX_MICROBLAZE0_INTERRUPT_IS_EDGE 0
define_int CONFIG_XILINX_MICROBLAZE0_EDGE_IS_POSITIVE 1
define_int CONFIG_XILINX_MICROBLAZE0_FSL_LINKS 0
define_int CONFIG_XILINX_MICROBLAZE0_FSL_DATA_SIZE 32
define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_BASEADDR 0x24000000
define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_HIGHADDR 0x25FFFFFF
define_int CONFIG_XILINX_MICROBLAZE0_USE_ICACHE 0
define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_ICACHE_WR 1
define_int CONFIG_XILINX_MICROBLAZE0_ADDR_TAG_BITS 0
define_int CONFIG_XILINX_MICROBLAZE0_CACHE_BYTE_SIZE 8192
define_int CONFIG_XILINX_MICROBLAZE0_ICACHE_USE_FSL 0
define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_BASEADDR 0x24000000
define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_HIGHADDR 0x25FFFFFF
define_int CONFIG_XILINX_MICROBLAZE0_USE_DCACHE 0
define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_DCACHE_WR 1
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_ADDR_TAG 0
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_BYTE_SIZE 8192
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_USE_FSL 0
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
define_string CONFIG_XILINX_MICROBLAZE0_HW_VER 4.00.b

# Definitions for LMB_BRAM_IF_CNTLR_0
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE dlmb_cntlr
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_BASEADDR 0x00000000
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HIGHADDR 0x0000FFFF
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_MASK 0x44000000
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_AWIDTH 32
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_DWIDTH 32
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE dlmb_cntlr
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HW_VER 2.00.a

# Definitions for LMB_BRAM_IF_CNTLR_1
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE ilmb_cntlr
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_BASEADDR 0x00000000
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HIGHADDR 0x0000FFFF
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_MASK 0x44000000
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_AWIDTH 32
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_DWIDTH 32
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE ilmb_cntlr
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HW_VER 2.00.a

# Definitions for V20_0
define_string CONFIG_XILINX_V20_0_INSTANCE mb_opb
define_hex CONFIG_XILINX_V20_0_BASEADDR 0xFFFFFFFF
define_hex CONFIG_XILINX_V20_0_HIGHADDR 0x00000000
define_int CONFIG_XILINX_V20_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_V20_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_V20_0_NUM_MASTERS 2
define_int CONFIG_XILINX_V20_0_NUM_SLAVES 10
define_int CONFIG_XILINX_V20_0_USE_LUT_OR 1
define_int CONFIG_XILINX_V20_0_EXT_RESET_HIGH 1
define_int CONFIG_XILINX_V20_0_DYNAM_PRIORITY 0
define_int CONFIG_XILINX_V20_0_PARK 0
define_int CONFIG_XILINX_V20_0_PROINTRFCE 0
define_int CONFIG_XILINX_V20_0_REG_GRANTS 1
define_int CONFIG_XILINX_V20_0_DEV_BLK_ID 0
define_int CONFIG_XILINX_V20_0_DEV_MIR_ENABLE 0
define_string CONFIG_XILINX_V20_0_INSTANCE mb_opb
define_string CONFIG_XILINX_V20_0_HW_VER 1.10.c

# Definitions for UARTLITE_0
define_string CONFIG_XILINX_UARTLITE_0_INSTANCE RS232
define_hex CONFIG_XILINX_UARTLITE_0_BASEADDR 0x40600000
define_hex CONFIG_XILINX_UARTLITE_0_HIGHADDR 0x4060FFFF
define_int CONFIG_XILINX_UARTLITE_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_UARTLITE_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_UARTLITE_0_DATA_BITS 8
define_int CONFIG_XILINX_UARTLITE_0_CLK_FREQ 100000000
define_int CONFIG_XILINX_UARTLITE_0_BAUDRATE 57600
define_int CONFIG_XILINX_UARTLITE_0_USE_PARITY 0
define_int CONFIG_XILINX_UARTLITE_0_ODD_PARITY 0
define_string CONFIG_XILINX_UARTLITE_0_INSTANCE RS232
define_string CONFIG_XILINX_UARTLITE_0_HW_VER 1.00.b
define_int CONFIG_XILINX_UARTLITE_0_IRQ 2

# Definitions for MDM_0
define_string CONFIG_XILINX_MDM_0_INSTANCE debug_module
define_hex CONFIG_XILINX_MDM_0_BASEADDR 0xFFFFC000
define_hex CONFIG_XILINX_MDM_0_HIGHADDR 0xFFFFC0FF
define_int CONFIG_XILINX_MDM_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_MDM_0_OPB_AWIDTH 32
define_string CONFIG_XILINX_MDM_0_FAMILY virtex4
define_int CONFIG_XILINX_MDM_0_MB_DBG_PORTS 1
define_int CONFIG_XILINX_MDM_0_USE_UART 1
define_int CONFIG_XILINX_MDM_0_UART_WIDTH 8
define_int CONFIG_XILINX_MDM_0_WRITE_FSL_PORTS 0
define_string CONFIG_XILINX_MDM_0_INSTANCE debug_module
define_string CONFIG_XILINX_MDM_0_HW_VER 2.00.a
define_int CONFIG_XILINX_MDM_0_IRQ 3

# Definitions for GPIO_0
define_string CONFIG_XILINX_GPIO_0_INSTANCE LEDs
define_hex CONFIG_XILINX_GPIO_0_BASEADDR 0x40000000
define_hex CONFIG_XILINX_GPIO_0_HIGHADDR 0x4000FFFF
define_int CONFIG_XILINX_GPIO_0_USER_ID_CODE 3
define_int CONFIG_XILINX_GPIO_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_GPIO_0_OPB_DWIDTH 32
define_string CONFIG_XILINX_GPIO_0_FAMILY virtex4
define_int CONFIG_XILINX_GPIO_0_GPIO_WIDTH 8
define_int CONFIG_XILINX_GPIO_0_ALL_INPUTS 0
define_int CONFIG_XILINX_GPIO_0_INTERRUPT_PRESENT 0
define_int CONFIG_XILINX_GPIO_0_IS_BIDIR 0
define_hex CONFIG_XILINX_GPIO_0_DOUT_DEFAULT 0x00000000
define_hex CONFIG_XILINX_GPIO_0_TRI_DEFAULT 0xFFFFFFFF
define_int CONFIG_XILINX_GPIO_0_IS_DUAL 0
define_int CONFIG_XILINX_GPIO_0_ALL_INPUTS_2 0
define_int CONFIG_XILINX_GPIO_0_IS_BIDIR_2 1
define_hex CONFIG_XILINX_GPIO_0_DOUT_DEFAULT_2 0x00000000
define_hex CONFIG_XILINX_GPIO_0_TRI_DEFAULT_2 0xFFFFFFFF
define_string CONFIG_XILINX_GPIO_0_INSTANCE LEDs
define_string CONFIG_XILINX_GPIO_0_HW_VER 3.01.b

# Definitions for GPIO_1
define_string CONFIG_XILINX_GPIO_1_INSTANCE Push_Button_SW4
define_hex CONFIG_XILINX_GPIO_1_BASEADDR 0x40020000
define_hex CONFIG_XILINX_GPIO_1_HIGHADDR 0x4002FFFF
define_int CONFIG_XILINX_GPIO_1_USER_ID_CODE 3
define_int CONFIG_XILINX_GPIO_1_OPB_AWIDTH 32
define_int CONFIG_XILINX_GPIO_1_OPB_DWIDTH 32
define_string CONFIG_XILINX_GPIO_1_FAMILY virtex4
define_int CONFIG_XILINX_GPIO_1_GPIO_WIDTH 1
define_int CONFIG_XILINX_GPIO_1_ALL_INPUTS 1
define_int CONFIG_XILINX_GPIO_1_INTERRUPT_PRESENT 0
define_int CONFIG_XILINX_GPIO_1_IS_BIDIR 0
define_hex CONFIG_XILINX_GPIO_1_DOUT_DEFAULT 0x00000000
define_hex CONFIG_XILINX_GPIO_1_TRI_DEFAULT 0xFFFFFFFF
define_int CONFIG_XILINX_GPIO_1_IS_DUAL 0
define_int CONFIG_XILINX_GPIO_1_ALL_INPUTS_2 0
define_int CONFIG_XILINX_GPIO_1_IS_BIDIR_2 1
define_hex CONFIG_XILINX_GPIO_1_DOUT_DEFAULT_2 0x00000000
define_hex CONFIG_XILINX_GPIO_1_TRI_DEFAULT_2 0xFFFFFFFF
define_string CONFIG_XILINX_GPIO_1_INSTANCE Push_Button_SW4
define_string CONFIG_XILINX_GPIO_1_HW_VER 3.01.b

# Definitions for GPIO_2
define_string CONFIG_XILINX_GPIO_2_INSTANCE DIP_Switches
define_hex CONFIG_XILINX_GPIO_2_BASEADDR 0x40040000
define_hex CONFIG_XILINX_GPIO_2_HIGHADDR 0x4004FFFF
define_int CONFIG_XILINX_GPIO_2_USER_ID_CODE 3
define_int CONFIG_XILINX_GPIO_2_OPB_AWIDTH 32
define_int CONFIG_XILINX_GPIO_2_OPB_DWIDTH 32
define_string CONFIG_XILINX_GPIO_2_FAMILY virtex4
define_int CONFIG_XILINX_GPIO_2_GPIO_WIDTH 8
define_int CONFIG_XILINX_GPIO_2_ALL_INPUTS 1
define_int CONFIG_XILINX_GPIO_2_INTERRUPT_PRESENT 0
define_int CONFIG_XILINX_GPIO_2_IS_BIDIR 0
define_hex CONFIG_XILINX_GPIO_2_DOUT_DEFAULT 0x00000000
define_hex CONFIG_XILINX_GPIO_2_TRI_DEFAULT 0xFFFFFFFF
define_int CONFIG_XILINX_GPIO_2_IS_DUAL 0
define_int CONFIG_XILINX_GPIO_2_ALL_INPUTS_2 0
define_int CONFIG_XILINX_GPIO_2_IS_BIDIR_2 1
define_hex CONFIG_XILINX_GPIO_2_DOUT_DEFAULT_2 0x00000000
define_hex CONFIG_XILINX_GPIO_2_TRI_DEFAULT_2 0xFFFFFFFF
define_string CONFIG_XILINX_GPIO_2_INSTANCE DIP_Switches
define_string CONFIG_XILINX_GPIO_2_HW_VER 3.01.b

# Definitions for DDR_0
define_string CONFIG_XILINX_DDR_0_INSTANCE DDR_SDRAM_16Mx16
define_int CONFIG_XILINX_DDR_0_DDR_ASYNSUPPORT 0
define_int CONFIG_XILINX_DDR_0_INCLUDE_BURST_SUPPORT 0
define_int CONFIG_XILINX_DDR_0_REG_DIMM 0
define_int CONFIG_XILINX_DDR_0_EXTRA_TSU 0
define_int CONFIG_XILINX_DDR_0_NUM_BANKS_MEM 1
define_int CONFIG_XILINX_DDR_0_NUM_CLK_PAIRS 2
define_string CONFIG_XILINX_DDR_0_FAMILY virtex4
define_int CONFIG_XILINX_DDR_0_DDR_TMRD 15000
define_int CONFIG_XILINX_DDR_0_DDR_TWR 15000
define_int CONFIG_XILINX_DDR_0_DDR_TWTR 1
define_int CONFIG_XILINX_DDR_0_DDR_TRAS 42000
define_int CONFIG_XILINX_DDR_0_DDR_TRC 65000
define_int CONFIG_XILINX_DDR_0_DDR_TRFC 75000
define_int CONFIG_XILINX_DDR_0_DDR_TRCD 20000
define_int CONFIG_XILINX_DDR_0_DDR_TRRD 15000
define_int CONFIG_XILINX_DDR_0_DDR_TREFC 70300000
define_int CONFIG_XILINX_DDR_0_DDR_TREFI 7800000
define_int CONFIG_XILINX_DDR_0_DDR_TRP 20000
define_int CONFIG_XILINX_DDR_0_DDR_CAS_LAT 2
define_int CONFIG_XILINX_DDR_0_DDR_DWIDTH 16
define_int CONFIG_XILINX_DDR_0_DDR_AWIDTH 13
define_int CONFIG_XILINX_DDR_0_DDR_COL_AWIDTH 9
define_int CONFIG_XILINX_DDR_0_DDR_BANK_AWIDTH 2
define_hex CONFIG_XILINX_DDR_0_MEM0_BASEADDR 0x24000000
define_hex CONFIG_XILINX_DDR_0_MEM0_HIGHADDR 0x25FFFFFF
define_hex CONFIG_XILINX_DDR_0_MEM1_BASEADDR 0xFFFFFFFF
define_hex CONFIG_XILINX_DDR_0_MEM1_HIGHADDR 0x00000000
define_hex CONFIG_XILINX_DDR_0_MEM2_BASEADDR 0xFFFFFFFF
define_hex CONFIG_XILINX_DDR_0_MEM2_HIGHADDR 0x00000000
define_hex CONFIG_XILINX_DDR_0_MEM3_BASEADDR 0xFFFFFFFF
define_hex CONFIG_XILINX_DDR_0_MEM3_HIGHADDR 0x00000000
define_int CONFIG_XILINX_DDR_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_DDR_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_DDR_0_OPB_CLK_PERIOD_PS 10000
define_int CONFIG_XILINX_DDR_0_SIM_INIT_TIME_PS 200000000
define_string CONFIG_XILINX_DDR_0_INSTANCE DDR_SDRAM_16Mx16
define_string CONFIG_XILINX_DDR_0_HW_VER 2.00.c

# Definitions for EMC_0
define_string CONFIG_XILINX_EMC_0_INSTANCE FLASH_4Mx16
define_int CONFIG_XILINX_EMC_0_NUM_BANKS_MEM 1
define_int CONFIG_XILINX_EMC_0_INCLUDE_BURST 0
define_int CONFIG_XILINX_EMC_0_INCLUDE_NEGEDGE_IOREGS 0
define_string CONFIG_XILINX_EMC_0_FAMILY virtex4
define_hex CONFIG_XILINX_EMC_0_MEM0_BASEADDR 0x26000000
define_hex CONFIG_XILINX_EMC_0_MEM0_HIGHADDR 0x267FFFFF
define_hex CONFIG_XILINX_EMC_0_MEM1_BASEADDR 0xFFFFFFFF
define_hex CONFIG_XILINX_EMC_0_MEM1_HIGHADDR 0x00000000
define_hex CONFIG_XILINX_EMC_0_MEM2_BASEADDR 0xFFFFFFFF
define_hex CONFIG_XILINX_EMC_0_MEM2_HIGHADDR 0x00000000
define_hex CONFIG_XILINX_EMC_0_MEM3_BASEADDR 0xFFFFFFFF
define_hex CONFIG_XILINX_EMC_0_MEM3_HIGHADDR 0x00000000
define_int CONFIG_XILINX_EMC_0_MEM0_WIDTH 16
define_int CONFIG_XILINX_EMC_0_MEM1_WIDTH 32
define_int CONFIG_XILINX_EMC_0_MEM2_WIDTH 32
define_int CONFIG_XILINX_EMC_0_MEM3_WIDTH 32
define_int CONFIG_XILINX_EMC_0_MAX_MEM_WIDTH 16
define_int CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_0 0
define_int CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_1 1
define_int CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_2 1
define_int CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_3 1
define_int CONFIG_XILINX_EMC_0_SYNCH_MEM_0 0
define_int CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_0 2
define_int CONFIG_XILINX_EMC_0_TCEDV_PS_MEM_0 120000
define_int CONFIG_XILINX_EMC_0_TAVDV_PS_MEM_0 120000
define_int CONFIG_XILINX_EMC_0_THZCE_PS_MEM_0 35000
define_int CONFIG_XILINX_EMC_0_THZOE_PS_MEM_0 7000
define_int CONFIG_XILINX_EMC_0_TWPS_MEM_0 120000
define_int CONFIG_XILINX_EMC_0_TWP_PS_MEM_0 120000
define_int CONFIG_XILINX_EMC_0_TLZWE_PS_MEM_0 35000
define_int CONFIG_XILINX_EMC_0_SYNCH_MEM_1 0
define_int CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_1 2
define_int CONFIG_XILINX_EMC_0_TCEDV_PS_MEM_1 15000
define_int CONFIG_XILINX_EMC_0_TAVDV_PS_MEM_1 15000
define_int CONFIG_XILINX_EMC_0_THZCE_PS_MEM_1 7000
define_int CONFIG_XILINX_EMC_0_THZOE_PS_MEM_1 7000
define_int CONFIG_XILINX_EMC_0_TWPS_MEM_1 15000
define_int CONFIG_XILINX_EMC_0_TWP_PS_MEM_1 12000
define_int CONFIG_XILINX_EMC_0_TLZWE_PS_MEM_1 0
define_int CONFIG_XILINX_EMC_0_SYNCH_MEM_2 0
define_int CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_2 2
define_int CONFIG_XILINX_EMC_0_TCEDV_PS_MEM_2 15000
define_int CONFIG_XILINX_EMC_0_TAVDV_PS_MEM_2 15000
define_int CONFIG_XILINX_EMC_0_THZCE_PS_MEM_2 7000
define_int CONFIG_XILINX_EMC_0_THZOE_PS_MEM_2 7000
define_int CONFIG_XILINX_EMC_0_TWPS_MEM_2 15000
define_int CONFIG_XILINX_EMC_0_TWP_PS_MEM_2 12000
define_int CONFIG_XILINX_EMC_0_TLZWE_PS_MEM_2 0
define_int CONFIG_XILINX_EMC_0_SYNCH_MEM_3 0
define_int CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_3 2
define_int CONFIG_XILINX_EMC_0_TCEDV_PS_MEM_3 15000
define_int CONFIG_XILINX_EMC_0_TAVDV_PS_MEM_3 15000
define_int CONFIG_XILINX_EMC_0_THZCE_PS_MEM_3 7000
define_int CONFIG_XILINX_EMC_0_THZOE_PS_MEM_3 7000
define_int CONFIG_XILINX_EMC_0_TWPS_MEM_3 15000
define_int CONFIG_XILINX_EMC_0_TWP_PS_MEM_3 12000
define_int CONFIG_XILINX_EMC_0_TLZWE_PS_MEM_3 0
define_int CONFIG_XILINX_EMC_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_EMC_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_EMC_0_OPB_CLK_PERIOD_PS 10000
define_string CONFIG_XILINX_EMC_0_INSTANCE FLASH_4Mx16
define_string CONFIG_XILINX_EMC_0_HW_VER 2.00.a

# Definitions for ETHERNET_0
define_string CONFIG_XILINX_ETHERNET_0_INSTANCE Ethernet_MAC
define_int CONFIG_XILINX_ETHERNET_0_DEV_BLK_ID 0
define_int CONFIG_XILINX_ETHERNET_0_DEV_MIR_ENABLE 1
define_hex CONFIG_XILINX_ETHERNET_0_BASEADDR 0x40C00000
define_hex CONFIG_XILINX_ETHERNET_0_HIGHADDR 0x40C0FFFF
define_int CONFIG_XILINX_ETHERNET_0_RESET_PRESENT 1
define_int CONFIG_XILINX_ETHERNET_0_INCLUDE_DEV_PENCODER 1
define_int CONFIG_XILINX_ETHERNET_0_DMA_PRESENT 1
define_int CONFIG_XILINX_ETHERNET_0_DMA_INTR_COALESCE 1
define_int CONFIG_XILINX_ETHERNET_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_ETHERNET_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_ETHERNET_0_OPB_CLK_PERIOD_PS 10000
define_string CONFIG_XILINX_ETHERNET_0_FAMILY virtex4
define_int CONFIG_XILINX_ETHERNET_0_IPIF_RDFIFO_DEPTH 32768
define_int CONFIG_XILINX_ETHERNET_0_IPIF_WRFIFO_DEPTH 32768
define_hex CONFIG_XILINX_ETHERNET_0_MIIM_CLKDVD 0x0000001F
define_int CONFIG_XILINX_ETHERNET_0_SOURCE_ADDR_INSERT_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_PAD_INSERT_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_FCS_INSERT_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_MAFIFO_DEPTH 64
define_int CONFIG_XILINX_ETHERNET_0_MAFIFO_BRAM_1_SRL_0 0
define_int CONFIG_XILINX_ETHERNET_0_HALF_DUPLEX_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_ERR_COUNT_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_CAM_EXIST 0
define_int CONFIG_XILINX_ETHERNET_0_CAM_BRAM_0_SRL_1 1
define_int CONFIG_XILINX_ETHERNET_0_JUMBO_EXIST 0
define_int CONFIG_XILINX_ETHERNET_0_MII_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_TX_DRE_TYPE 0
define_int CONFIG_XILINX_ETHERNET_0_RX_DRE_TYPE 0
define_int CONFIG_XILINX_ETHERNET_0_TX_INCLUDE_CSUM 0
define_int CONFIG_XILINX_ETHERNET_0_RX_INCLUDE_CSUM 0
define_string CONFIG_XILINX_ETHERNET_0_INSTANCE Ethernet_MAC
define_string CONFIG_XILINX_ETHERNET_0_HW_VER 1.04.a
define_int CONFIG_XILINX_ETHERNET_0_IRQ 1

# Definitions for TIMER_0
define_string CONFIG_XILINX_TIMER_0_INSTANCE opb_timer_1
define_string CONFIG_XILINX_TIMER_0_FAMILY virtex4
define_int CONFIG_XILINX_TIMER_0_COUNT_WIDTH 32
define_int CONFIG_XILINX_TIMER_0_ONE_TIMER_ONLY 1
define_int CONFIG_XILINX_TIMER_0_TRIG0_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_TRIG1_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_GEN0_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_GEN1_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_TIMER_0_OPB_DWIDTH 32
define_hex CONFIG_XILINX_TIMER_0_BASEADDR 0x41C00000
define_hex CONFIG_XILINX_TIMER_0_HIGHADDR 0x41C0FFFF
define_string CONFIG_XILINX_TIMER_0_INSTANCE opb_timer_1
define_string CONFIG_XILINX_TIMER_0_HW_VER 1.00.b
define_int CONFIG_XILINX_TIMER_0_IRQ 0

# Definitions for INTC_0
define_string CONFIG_XILINX_INTC_0_INSTANCE opb_intc_0
define_string CONFIG_XILINX_INTC_0_FAMILY virtex4
define_int CONFIG_XILINX_INTC_0_Y 0
define_int CONFIG_XILINX_INTC_0_X 0
define_string CONFIG_XILINX_INTC_0_U_SET intc
define_int CONFIG_XILINX_INTC_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_INTC_0_OPB_DWIDTH 32
define_hex CONFIG_XILINX_INTC_0_BASEADDR 0x41200000
define_hex CONFIG_XILINX_INTC_0_HIGHADDR 0x4120FFFF
define_int CONFIG_XILINX_INTC_0_NUM_INTR_INPUTS 4
define_hex CONFIG_XILINX_INTC_0_KIND_OF_INTR 0x0000000C
define_hex CONFIG_XILINX_INTC_0_KIND_OF_EDGE 0x0000000C
define_hex CONFIG_XILINX_INTC_0_KIND_OF_LVL 0x00000003
define_int CONFIG_XILINX_INTC_0_HAS_IPR 1
define_int CONFIG_XILINX_INTC_0_HAS_SIE 1
define_int CONFIG_XILINX_INTC_0_HAS_CIE 1
define_int CONFIG_XILINX_INTC_0_HAS_IVR 1
define_int CONFIG_XILINX_INTC_0_IRQ_IS_LEVEL 1
define_int CONFIG_XILINX_INTC_0_IRQ_ACTIVE 1
define_string CONFIG_XILINX_INTC_0_INSTANCE opb_intc_0
define_string CONFIG_XILINX_INTC_0_HW_VER 1.00.c

# Peripheral counts
define_int CONFIG_XILINX_V20_NUM_INSTANCES 1
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_NUM_INSTANCES 2
define_int CONFIG_XILINX_TIMER_NUM_INSTANCES 1
define_int CONFIG_XILINX_EMC_NUM_INSTANCES 1
define_int CONFIG_XILINX_INTC_NUM_INSTANCES 1
define_int CONFIG_XILINX_DDR_NUM_INSTANCES 1
define_int CONFIG_XILINX_MDM_NUM_INSTANCES 1
define_int CONFIG_XILINX_UARTLITE_NUM_INSTANCES 1
define_int CONFIG_XILINX_ETHERNET_NUM_INSTANCES 1
define_int CONFIG_XILINX_GPIO_NUM_INSTANCES 3

=== END auto-config.in

--
Ryan Marotz <rmarotz@xxxxxxxxxx>
Architecture Technology Corp
952.829.5864 x160
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