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[microblaze-uclinux] error setting up sdram memory
All,
I have a dual MicroBlaze configuration on an Avnet Virtex-4 LX
evaluation Board (LX60) v1.0. My first MicroBlaze (microblaze_0) uses
the main board ddr memory (sdram_0) and PHY (ethernet_0). The second
MicroBlaze (microblaze_1) uses a daughter card sdram (sdram_1) and PHY
(ethernet_1). I'm getting an error during the software compile in
Xilinx Platform Studio (see error below). The error seems associated
with the daughter card sdram. If I connect sdram_1 to microblaze_0 and
sdram_0 to microblaze_1, the error occurs during compile of
microblaze_0. Any thoughts? Thanks in advance for the help. I've
attached the ucf, mhs, and mss files.
#--------------------------------------
# uClinux BSP generate...
#--------------------------------------
ERROR:MDT - uclinux () - expected integer but got ""
while executing
"format "0x%08x" $mem_start"
(procedure "do_memory_setup" line 64)
invoked from within
"do_memory_setup $config_file $os_handle "MAIN_MEMORY"
CONFIG_XILINX_ERAM"
(procedure "::sw_uclinux_v1_00_d::generate" line 22)
invoked from within
"::sw_uclinux_v1_00_d::generate 45333696"
ERROR:MDT - Error while running "generate" for processor microblaze_1...
-Ryan
############################################################################
## This system.ucf file is generated by Base System Builder based on the
## settings in the selected Xilinx Board Definition file. Please add other
## user constraints to this file based on customer design specifications.
############################################################################
Net sys_clk_pin LOC=C13;
Net sys_clk_pin IOSTANDARD = LVCMOS33;
Net sys_rst_pin LOC=L3;
## System level constraints
Net sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps;
Net sys_rst_pin TIG;
Net fpga_0_DDR_CLK_FB LOC=AB10;
Net fpga_0_DDR_CLK_FB IOSTANDARD = LVCMOS25;
## IO Devices constraints
#### Module RS232 constraints
Net fpga_0_RS232_0_RX_pin LOC=AC1;
Net fpga_0_RS232_0_TX_pin LOC=AB1;
#### Module LEDs constraints
Net fpga_0_LEDs_GPIO_IO_pin<0> LOC=AC6;
Net fpga_0_LEDs_GPIO_IO_pin<1> LOC=AD6;
Net fpga_0_LEDs_GPIO_IO_pin<2> LOC=AF6;
Net fpga_0_LEDs_GPIO_IO_pin<3> LOC=AE6;
Net fpga_0_LEDs_GPIO_IO_pin<4> LOC=AD5;
Net fpga_0_LEDs_GPIO_IO_pin<5> LOC=AE4;
Net fpga_0_LEDs_GPIO_IO_pin<6> LOC=AF4;
Net fpga_0_LEDs_GPIO_IO_pin<7> LOC=AF3;
#### Module Push_Button_SW4 constraints
Net fpga_0_Push_Button_SW4_GPIO_in_pin<0> LOC=T1;
#### Module DIP_Switches constraints
Net fpga_0_DIP_Switches_GPIO_in_pin<0> LOC=R7;
Net fpga_0_DIP_Switches_GPIO_in_pin<1> LOC=T6;
Net fpga_0_DIP_Switches_GPIO_in_pin<2> LOC=U3;
Net fpga_0_DIP_Switches_GPIO_in_pin<3> LOC=U4;
Net fpga_0_DIP_Switches_GPIO_in_pin<4> LOC=V4;
Net fpga_0_DIP_Switches_GPIO_in_pin<5> LOC=M8;
Net fpga_0_DIP_Switches_GPIO_in_pin<6> LOC=L8;
#Net fpga_0_DIP_Switches_GPIO_in_pin<7> LOC=H20;
#### Module sdram_0 constraints
Net fpga_0_sdram_0_DDR_Clk_pin<0> LOC=T4;
Net fpga_0_sdram_0_DDR_Clk_pin<0> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_Clkn_pin<0> LOC=T3;
Net fpga_0_sdram_0_DDR_Clkn_pin<0> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_Clk_pin<1> LOC=T7;
Net fpga_0_sdram_0_DDR_Clk_pin<1> IOSTANDARD = LVCMOS25;
Net fpga_0_sdram_0_DDR_Clkn_pin<1> LOC=T8;
Net fpga_0_sdram_0_DDR_Clkn_pin<1> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_Addr_pin<12> LOC=L1;
Net fpga_0_sdram_0_DDR_Addr_pin<12> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_Addr_pin<11> LOC=K1;
Net fpga_0_sdram_0_DDR_Addr_pin<11> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_Addr_pin<10> LOC=J4;
Net fpga_0_sdram_0_DDR_Addr_pin<10> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_Addr_pin<9> LOC=J2;
Net fpga_0_sdram_0_DDR_Addr_pin<9> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_Addr_pin<8> LOC=J5;
Net fpga_0_sdram_0_DDR_Addr_pin<8> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_Addr_pin<7> LOC=J6;
Net fpga_0_sdram_0_DDR_Addr_pin<7> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_Addr_pin<6> LOC=J7;
Net fpga_0_sdram_0_DDR_Addr_pin<6> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_Addr_pin<5> LOC=M7;
Net fpga_0_sdram_0_DDR_Addr_pin<5> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_Addr_pin<4> LOC=M6;
Net fpga_0_sdram_0_DDR_Addr_pin<4> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_Addr_pin<3> LOC=M5;
Net fpga_0_sdram_0_DDR_Addr_pin<3> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_Addr_pin<2> LOC=M1;
Net fpga_0_sdram_0_DDR_Addr_pin<2> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_Addr_pin<1> LOC=N7;
Net fpga_0_sdram_0_DDR_Addr_pin<1> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_Addr_pin<0> LOC=R4;
Net fpga_0_sdram_0_DDR_Addr_pin<0> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_BankAddr_pin<1> LOC=M4;
Net fpga_0_sdram_0_DDR_BankAddr_pin<1> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_BankAddr_pin<0> LOC=M2;
Net fpga_0_sdram_0_DDR_BankAddr_pin<0> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_CASn_pin LOC=P2;
Net fpga_0_sdram_0_DDR_CASn_pin IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_CKE_pin LOC=N5;
Net fpga_0_sdram_0_DDR_CKE_pin IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_CSn_pin LOC=N3;
Net fpga_0_sdram_0_DDR_CSn_pin IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_RASn_pin LOC=N2;
Net fpga_0_sdram_0_DDR_RASn_pin IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_WEn_pin LOC=N4;
Net fpga_0_sdram_0_DDR_WEn_pin IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_DM_pin<1> LOC=P4;
Net fpga_0_sdram_0_DDR_DM_pin<1> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_DM_pin<0> LOC=K7;
Net fpga_0_sdram_0_DDR_DM_pin<0> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_DQS_pin<1> LOC=L4;
Net fpga_0_sdram_0_DDR_DQS_pin<1> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_DQS_pin<0> LOC=U1;
Net fpga_0_sdram_0_DDR_DQS_pin<0> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_DQ_pin<15> LOC=V1;
Net fpga_0_sdram_0_DDR_DQ_pin<15> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_DQ_pin<14> LOC=V2;
Net fpga_0_sdram_0_DDR_DQ_pin<14> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_DQ_pin<13> LOC=R2;
Net fpga_0_sdram_0_DDR_DQ_pin<13> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_DQ_pin<12> LOC=P5;
Net fpga_0_sdram_0_DDR_DQ_pin<12> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_DQ_pin<11> LOC=R1;
Net fpga_0_sdram_0_DDR_DQ_pin<11> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_DQ_pin<10> LOC=K2;
Net fpga_0_sdram_0_DDR_DQ_pin<10> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_DQ_pin<9> LOC=K3;
Net fpga_0_sdram_0_DDR_DQ_pin<9> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_DQ_pin<8> LOC=K4;
Net fpga_0_sdram_0_DDR_DQ_pin<8> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_DQ_pin<7> LOC=K6;
Net fpga_0_sdram_0_DDR_DQ_pin<7> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_DQ_pin<6> LOC=K5;
Net fpga_0_sdram_0_DDR_DQ_pin<6> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_DQ_pin<5> LOC=L6;
Net fpga_0_sdram_0_DDR_DQ_pin<5> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_DQ_pin<4> LOC=L7;
Net fpga_0_sdram_0_DDR_DQ_pin<4> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_DQ_pin<3> LOC=N8;
Net fpga_0_sdram_0_DDR_DQ_pin<3> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_DQ_pin<2> LOC=P6;
Net fpga_0_sdram_0_DDR_DQ_pin<2> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_DQ_pin<1> LOC=P7;
Net fpga_0_sdram_0_DDR_DQ_pin<1> IOSTANDARD = SSTL2_I;
Net fpga_0_sdram_0_DDR_DQ_pin<0> LOC=P8;
Net fpga_0_sdram_0_DDR_DQ_pin<0> IOSTANDARD = SSTL2_I;
#### Module FLASH_4Mx16 constraints
Net fpga_0_FLASH_4Mx16_Mem_A_pin<30> LOC=AA18;
Net fpga_0_FLASH_4Mx16_Mem_A_pin<29> LOC=Y18;
Net fpga_0_FLASH_4Mx16_Mem_A_pin<28> LOC=AB23;
Net fpga_0_FLASH_4Mx16_Mem_A_pin<27> LOC=AF19;
Net fpga_0_FLASH_4Mx16_Mem_A_pin<26> LOC=AA23;
Net fpga_0_FLASH_4Mx16_Mem_A_pin<25> LOC=AF20;
Net fpga_0_FLASH_4Mx16_Mem_A_pin<24> LOC=AA24;
Net fpga_0_FLASH_4Mx16_Mem_A_pin<23> LOC=Y19;
Net fpga_0_FLASH_4Mx16_Mem_A_pin<22> LOC=Y23;
Net fpga_0_FLASH_4Mx16_Mem_A_pin<21> LOC=W19;
Net fpga_0_FLASH_4Mx16_Mem_A_pin<20> LOC=Y24;
Net fpga_0_FLASH_4Mx16_Mem_A_pin<19> LOC=W20;
Net fpga_0_FLASH_4Mx16_Mem_A_pin<18> LOC=Y25;
Net fpga_0_FLASH_4Mx16_Mem_A_pin<17> LOC=V20;
Net fpga_0_FLASH_4Mx16_Mem_A_pin<16> LOC=AA26;
Net fpga_0_FLASH_4Mx16_Mem_A_pin<15> LOC=AD22;
Net fpga_0_FLASH_4Mx16_Mem_A_pin<14> LOC=Y26;
Net fpga_0_FLASH_4Mx16_Mem_A_pin<13> LOC=AC22;
Net fpga_0_FLASH_4Mx16_Mem_A_pin<12> LOC=W25;
Net fpga_0_FLASH_4Mx16_Mem_A_pin<11> LOC=W23;
Net fpga_0_FLASH_4Mx16_Mem_A_pin<10> LOC=W26;
Net fpga_0_FLASH_4Mx16_Mem_A_pin<9> LOC=W24;
Net fpga_0_FLASH_4Mx16_Mem_DQ_pin<15> LOC=W21;
Net fpga_0_FLASH_4Mx16_Mem_DQ_pin<14> LOC=W22;
Net fpga_0_FLASH_4Mx16_Mem_DQ_pin<13> LOC=Y22;
Net fpga_0_FLASH_4Mx16_Mem_DQ_pin<12> LOC=AE23;
Net fpga_0_FLASH_4Mx16_Mem_DQ_pin<11> LOC=AC23;
Net fpga_0_FLASH_4Mx16_Mem_DQ_pin<10> LOC=AD25;
Net fpga_0_FLASH_4Mx16_Mem_DQ_pin<9> LOC=AD26;
Net fpga_0_FLASH_4Mx16_Mem_DQ_pin<8> LOC=AB24;
Net fpga_0_FLASH_4Mx16_Mem_DQ_pin<7> LOC=V21;
Net fpga_0_FLASH_4Mx16_Mem_DQ_pin<6> LOC=V22;
Net fpga_0_FLASH_4Mx16_Mem_DQ_pin<5> LOC=AB22;
Net fpga_0_FLASH_4Mx16_Mem_DQ_pin<4> LOC=AF23;
Net fpga_0_FLASH_4Mx16_Mem_DQ_pin<3> LOC=AD23;
Net fpga_0_FLASH_4Mx16_Mem_DQ_pin<2> LOC=AC24;
Net fpga_0_FLASH_4Mx16_Mem_DQ_pin<1> LOC=AC25;
Net fpga_0_FLASH_4Mx16_Mem_DQ_pin<0> LOC=AC26;
Net fpga_0_FLASH_4Mx16_Mem_WEN_pin LOC=AB26;
Net fpga_0_FLASH_4Mx16_Mem_OEN_pin<0> LOC=AB25;
Net fpga_0_FLASH_4Mx16_Mem_CEN_pin<0> LOC=Y20;
Net fpga_0_FLASH_4Mx16_Mem_RPN_pin LOC=Y21;
#### Module ethernet_0 constraints
Net fpga_0_ethernet_0_PHY_tx_clk_pin LOC=Y4;
Net fpga_0_ethernet_0_PHY_tx_clk_pin PERIOD=40000 ps;
Net fpga_0_ethernet_0_PHY_rx_clk_pin LOC=Y5;
Net fpga_0_ethernet_0_PHY_rx_clk_pin PERIOD=40000 ps;
Net fpga_0_ethernet_0_PHY_crs_pin LOC=AE3;
Net fpga_0_ethernet_0_PHY_crs_pin IOBDELAY=NONE;
Net fpga_0_ethernet_0_PHY_dv_pin LOC=Y3;
Net fpga_0_ethernet_0_PHY_dv_pin IOBDELAY=NONE;
Net fpga_0_ethernet_0_PHY_rx_data_pin<0> LOC=W4;
Net fpga_0_ethernet_0_PHY_rx_data_pin<0> IOBDELAY=NONE;
Net fpga_0_ethernet_0_PHY_rx_data_pin<1> LOC=W3;
Net fpga_0_ethernet_0_PHY_rx_data_pin<1> IOBDELAY=NONE;
Net fpga_0_ethernet_0_PHY_rx_data_pin<2> LOC=W1;
Net fpga_0_ethernet_0_PHY_rx_data_pin<2> IOBDELAY=NONE;
Net fpga_0_ethernet_0_PHY_rx_data_pin<3> LOC=W2;
Net fpga_0_ethernet_0_PHY_rx_data_pin<3> IOBDELAY=NONE;
Net fpga_0_ethernet_0_PHY_col_pin LOC=AD4;
Net fpga_0_ethernet_0_PHY_col_pin IOBDELAY=NONE;
Net fpga_0_ethernet_0_PHY_rx_er_pin LOC=AA3;
Net fpga_0_ethernet_0_PHY_rx_er_pin IOBDELAY=NONE;
Net fpga_0_ethernet_0_PHY_tx_en_pin LOC=AC2;
Net fpga_0_ethernet_0_PHY_tx_data_pin<0> LOC=AC3;
Net fpga_0_ethernet_0_PHY_tx_data_pin<1> LOC=AC4;
Net fpga_0_ethernet_0_PHY_tx_data_pin<2> LOC=AD1;
Net fpga_0_ethernet_0_PHY_tx_data_pin<3> LOC=AD2;
Net fpga_0_ethernet_0_PHY_Mii_clk_pin LOC=V5;
Net fpga_0_ethernet_0_PHY_Mii_data_pin LOC=V6;
Net fpga_0_ethernet_0_PHY_tx_er_pin LOC=AA4;
Net fpga_0_ethernet_0_PHY_tx_er_pin IOBDELAY=NONE;
Net fpga_0_ethernet_0_PHY_rst_n_pin LOC=AF24;
Net fpga_0_DDR_CLK_FB TNM_NET = fpga_0_DDR_CLK_FB;
TIMESPEC TS_fpga_0_DDR_CLK_FB = PERIOD fpga_0_DDR_CLK_FB 10000 ps;
#### Module sdram_1 constraints
Net fpga_0_sdram_1_SDRAM_Addr_pin<0> LOC=F3;
Net fpga_0_sdram_1_SDRAM_Addr_pin<0> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_Addr_pin<1> LOC=F1;
Net fpga_0_sdram_1_SDRAM_Addr_pin<1> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_Addr_pin<2> LOC=G3;
Net fpga_0_sdram_1_SDRAM_Addr_pin<2> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_Addr_pin<3> LOC=G2;
Net fpga_0_sdram_1_SDRAM_Addr_pin<3> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_Addr_pin<4> LOC=G5;
Net fpga_0_sdram_1_SDRAM_Addr_pin<4> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_Addr_pin<5> LOC=G4;
Net fpga_0_sdram_1_SDRAM_Addr_pin<5> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_Addr_pin<6> LOC=G1;
Net fpga_0_sdram_1_SDRAM_Addr_pin<6> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_Addr_pin<7> LOC=H2;
Net fpga_0_sdram_1_SDRAM_Addr_pin<7> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_Addr_pin<8> LOC=H4;
Net fpga_0_sdram_1_SDRAM_Addr_pin<8> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_Addr_pin<9> LOC=H3;
Net fpga_0_sdram_1_SDRAM_Addr_pin<9> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_Addr_pin<10> LOC=H1;
Net fpga_0_sdram_1_SDRAM_Addr_pin<10> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_Addr_pin<11> LOC=H7;
Net fpga_0_sdram_1_SDRAM_Addr_pin<11> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_Addr_pin<12> LOC=H5;
Net fpga_0_sdram_1_SDRAM_Addr_pin<12> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_BankAddr_pin<0> LOC=G7;
Net fpga_0_sdram_1_SDRAM_BankAddr_pin<0> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_BankAddr_pin<1> LOC=G6;
Net fpga_0_sdram_1_SDRAM_BankAddr_pin<1> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<0> LOC=C11;
Net fpga_0_sdram_1_SDRAM_DQ_pin<0> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<1> LOC=D11;
Net fpga_0_sdram_1_SDRAM_DQ_pin<1> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<2> LOC=A11;
Net fpga_0_sdram_1_SDRAM_DQ_pin<2> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<3> LOC=F10;
Net fpga_0_sdram_1_SDRAM_DQ_pin<3> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<4> LOC=D10;
Net fpga_0_sdram_1_SDRAM_DQ_pin<4> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<5> LOC=E10;
Net fpga_0_sdram_1_SDRAM_DQ_pin<5> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<6> LOC=C10;
Net fpga_0_sdram_1_SDRAM_DQ_pin<6> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<7> LOC=D9;
Net fpga_0_sdram_1_SDRAM_DQ_pin<7> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<8> LOC=B9;
Net fpga_0_sdram_1_SDRAM_DQ_pin<8> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<9> LOC=F9;
Net fpga_0_sdram_1_SDRAM_DQ_pin<9> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<10> LOC=E9;
Net fpga_0_sdram_1_SDRAM_DQ_pin<10> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<11> LOC=A9;
Net fpga_0_sdram_1_SDRAM_DQ_pin<11> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<12> LOC=D8;
Net fpga_0_sdram_1_SDRAM_DQ_pin<12> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<13> LOC=F8;
Net fpga_0_sdram_1_SDRAM_DQ_pin<13> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<14> LOC=F7;
Net fpga_0_sdram_1_SDRAM_DQ_pin<14> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<15> LOC=C8;
Net fpga_0_sdram_1_SDRAM_DQ_pin<15> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<16> LOC=E7;
Net fpga_0_sdram_1_SDRAM_DQ_pin<16> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<17> LOC=A8;
Net fpga_0_sdram_1_SDRAM_DQ_pin<17> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<18> LOC=C7;
Net fpga_0_sdram_1_SDRAM_DQ_pin<18> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<19> LOC=D7;
Net fpga_0_sdram_1_SDRAM_DQ_pin<19> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<20> LOC=C6;
Net fpga_0_sdram_1_SDRAM_DQ_pin<20> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<21> LOC=B7;
Net fpga_0_sdram_1_SDRAM_DQ_pin<21> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<22> LOC=A7;
Net fpga_0_sdram_1_SDRAM_DQ_pin<22> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<23> LOC=B6;
Net fpga_0_sdram_1_SDRAM_DQ_pin<23> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<24> LOC=A6;
Net fpga_0_sdram_1_SDRAM_DQ_pin<24> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<25> LOC=E6;
Net fpga_0_sdram_1_SDRAM_DQ_pin<25> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<26> LOC=D6;
Net fpga_0_sdram_1_SDRAM_DQ_pin<26> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<27> LOC=C5;
Net fpga_0_sdram_1_SDRAM_DQ_pin<27> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<28> LOC=A5;
Net fpga_0_sdram_1_SDRAM_DQ_pin<28> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<29> LOC=E5;
Net fpga_0_sdram_1_SDRAM_DQ_pin<29> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<30> LOC=D5;
Net fpga_0_sdram_1_SDRAM_DQ_pin<30> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQ_pin<31> LOC=B4;
Net fpga_0_sdram_1_SDRAM_DQ_pin<31> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_WEn_pin LOC=A12;
Net fpga_0_sdram_1_SDRAM_WEn_pin IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_CSn_pin LOC=G9;
Net fpga_0_sdram_1_SDRAM_CSn_pin IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_CASn_pin LOC=D13;
Net fpga_0_sdram_1_SDRAM_CASn_pin IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_RASn_pin LOC=E13;
Net fpga_0_sdram_1_SDRAM_RASn_pin IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_CKE_pin LOC=D14;
Net fpga_0_sdram_1_SDRAM_CKE_pin IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_Clk_pin LOC=F13;
Net fpga_0_sdram_1_SDRAM_Clk_pin IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQM_pin<0> LOC=F15;
Net fpga_0_sdram_1_SDRAM_DQM_pin<0> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQM_pin<1> LOC=F14;
Net fpga_0_sdram_1_SDRAM_DQM_pin<1> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQM_pin<2> LOC=E14;
Net fpga_0_sdram_1_SDRAM_DQM_pin<2> IOSTANDARD = LVCMOS33;
Net fpga_0_sdram_1_SDRAM_DQM_pin<3> LOC=B14;
Net fpga_0_sdram_1_SDRAM_DQM_pin<3> IOSTANDARD = LVCMOS33;
#### Module ethernet_1 constraints
Net fpga_0_ethernet_1_PHY_rst_n_pin LOC=K24;
Net fpga_0_ethernet_1_PHY_rst_n_pin IOSTANDARD = LVCMOS33;
Net fpga_0_ethernet_1_PHY_Mii_clk_pin LOC=A24;
Net fpga_0_ethernet_1_PHY_Mii_clk_pin IOSTANDARD = LVCMOS33;
Net fpga_0_ethernet_1_PHY_Mii_data_pin LOC=C23;
Net fpga_0_ethernet_1_PHY_Mii_data_pin IOSTANDARD = LVCMOS33;
Net fpga_0_ethernet_1_PHY_crs_pin LOC=E22;
Net fpga_0_ethernet_1_PHY_crs_pin IOSTANDARD = LVCMOS33;
Net fpga_0_ethernet_1_PHY_col_pin LOC=D23;
Net fpga_0_ethernet_1_PHY_col_pin IOSTANDARD = LVCMOS33;
Net fpga_0_ethernet_1_PHY_rx_er_pin LOC=B24;
Net fpga_0_ethernet_1_PHY_rx_er_pin IOSTANDARD = LVCMOS33;
Net fpga_0_ethernet_1_PHY_rx_clk_pin LOC=B23;
Net fpga_0_ethernet_1_PHY_rx_clk_pin IOSTANDARD = LVCMOS33;
Net fpga_0_ethernet_1_PHY_rx_data_pin<3> LOC=C26;
Net fpga_0_ethernet_1_PHY_rx_data_pin<3> IOSTANDARD = LVCMOS33;
Net fpga_0_ethernet_1_PHY_rx_data_pin<2> LOC=G24;
Net fpga_0_ethernet_1_PHY_rx_data_pin<2> IOSTANDARD = LVCMOS33;
Net fpga_0_ethernet_1_PHY_rx_data_pin<1> LOC=D22;
Net fpga_0_ethernet_1_PHY_rx_data_pin<1> IOSTANDARD = LVCMOS33;
Net fpga_0_ethernet_1_PHY_rx_data_pin<0> LOC=H23;
Net fpga_0_ethernet_1_PHY_rx_data_pin<0> IOSTANDARD = LVCMOS33;
Net fpga_0_ethernet_1_PHY_dv_pin LOC=G21;
Net fpga_0_ethernet_1_PHY_dv_pin IOSTANDARD = LVCMOS33;
Net fpga_0_ethernet_1_PHY_tx_er_pin LOC=H24;
Net fpga_0_ethernet_1_PHY_tx_er_pin IOSTANDARD = LVCMOS33;
Net fpga_0_ethernet_1_PHY_tx_clk_pin LOC=C22;
Net fpga_0_ethernet_1_PHY_tx_clk_pin IOSTANDARD = LVCMOS33;
Net fpga_0_ethernet_1_PHY_tx_en_pin LOC=C24;
Net fpga_0_ethernet_1_PHY_tx_en_pin IOSTANDARD = LVCMOS33;
Net fpga_0_ethernet_1_PHY_tx_data_pin<3> LOC=D26;
Net fpga_0_ethernet_1_PHY_tx_data_pin<3> IOSTANDARD = LVCMOS33;
Net fpga_0_ethernet_1_PHY_tx_data_pin<2> LOC=E25;
Net fpga_0_ethernet_1_PHY_tx_data_pin<2> IOSTANDARD = LVCMOS33;
Net fpga_0_ethernet_1_PHY_tx_data_pin<1> LOC=F26;
Net fpga_0_ethernet_1_PHY_tx_data_pin<1> IOSTANDARD = LVCMOS33;
Net fpga_0_ethernet_1_PHY_tx_data_pin<0> LOC=E26;
Net fpga_0_ethernet_1_PHY_tx_data_pin<0> IOSTANDARD = LVCMOS33;
# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 8.2.02 Build EDK_Im_Sp2.4
# Fri Jun 22 10:34:43 2007
# Target Board: Avnet Virtex-4 LX Evaluation Board (LX60) Rev 1.0
# Family: virtex4
# Device: XC4VLX60
# Package: FF668
# Speed Grade: -10
# Processor: Microblaze
# System clock frequency: 100.000000 MHz
# Debug interface: On-Chip HW Debug Module
# On Chip Memory : 16 KB
# Total Off Chip Memory : 40 MB
# - DDR_SDRAM_16Mx16 = 32 MB
# - FLASH_4Mx16 = 8 MB
# ##############################################################################
PARAMETER VERSION = 2.1.0
PORT fpga_0_RS232_0_RX_pin = fpga_0_RS232_0_RX, DIR = I
PORT fpga_0_RS232_0_TX_pin = fpga_0_RS232_0_TX, DIR = O
PORT fpga_0_LEDs_GPIO_IO_pin = fpga_0_LEDs_GPIO_IO, DIR = IO, VEC = [0:7]
PORT fpga_0_Push_Button_SW4_GPIO_in_pin = fpga_0_Push_Button_SW4_GPIO_in, DIR = I, VEC = [0:0]
PORT fpga_0_DIP_Switches_GPIO_in_pin = fpga_0_DIP_Switches_GPIO_in, DIR = I, VEC = [0:7]
PORT fpga_0_sdram_0_DDR_Clk_pin = fpga_0_sdram_0_DDR_Clk, DIR = O, VEC = [0:1]
PORT fpga_0_sdram_0_DDR_Clkn_pin = fpga_0_sdram_0_DDR_Clkn, DIR = O, VEC = [0:1]
PORT fpga_0_sdram_0_DDR_Addr_pin = fpga_0_sdram_0_DDR_Addr, DIR = O, VEC = [0:12]
PORT fpga_0_sdram_0_DDR_BankAddr_pin = fpga_0_sdram_0_DDR_BankAddr, DIR = O, VEC = [0:1]
PORT fpga_0_sdram_0_DDR_CASn_pin = fpga_0_sdram_0_DDR_CASn, DIR = O
PORT fpga_0_sdram_0_DDR_CKE_pin = fpga_0_sdram_0_DDR_CKE, DIR = O
PORT fpga_0_sdram_0_DDR_CSn_pin = fpga_0_sdram_0_DDR_CSn, DIR = O
PORT fpga_0_sdram_0_DDR_RASn_pin = fpga_0_sdram_0_DDR_RASn, DIR = O
PORT fpga_0_sdram_0_DDR_WEn_pin = fpga_0_sdram_0_DDR_WEn, DIR = O
PORT fpga_0_sdram_0_DDR_DM_pin = fpga_0_sdram_0_DDR_DM, DIR = O, VEC = [0:1]
PORT fpga_0_sdram_0_DDR_DQS_pin = fpga_0_sdram_0_DDR_DQS, DIR = IO, VEC = [0:1]
PORT fpga_0_sdram_0_DDR_DQ_pin = fpga_0_sdram_0_DDR_DQ, DIR = IO, VEC = [0:15]
PORT fpga_0_FLASH_4Mx16_Mem_DQ_pin = fpga_0_FLASH_4Mx16_Mem_DQ, DIR = IO, VEC = [0:15]
PORT fpga_0_FLASH_4Mx16_Mem_A_pin = fpga_0_FLASH_4Mx16_Mem_A, DIR = O, VEC = [9:30]
PORT fpga_0_FLASH_4Mx16_Mem_WEN_pin = fpga_0_FLASH_4Mx16_Mem_WEN, DIR = O
PORT fpga_0_FLASH_4Mx16_Mem_OEN_pin = fpga_0_FLASH_4Mx16_Mem_OEN, DIR = O, VEC = [0:0]
PORT fpga_0_FLASH_4Mx16_Mem_CEN_pin = fpga_0_FLASH_4Mx16_Mem_CEN, DIR = O, VEC = [0:0]
PORT fpga_0_FLASH_4Mx16_Mem_RPN_pin = fpga_0_FLASH_4Mx16_Mem_RPN, DIR = O
PORT fpga_0_ethernet_0_PHY_tx_clk_pin = fpga_0_ethernet_0_PHY_tx_clk, DIR = I
PORT fpga_0_ethernet_0_PHY_rx_clk_pin = fpga_0_ethernet_0_PHY_rx_clk, DIR = I
PORT fpga_0_ethernet_0_PHY_crs_pin = fpga_0_ethernet_0_PHY_crs, DIR = I
PORT fpga_0_ethernet_0_PHY_dv_pin = fpga_0_ethernet_0_PHY_dv, DIR = I
PORT fpga_0_ethernet_0_PHY_rx_data_pin = fpga_0_ethernet_0_PHY_rx_data, DIR = I, VEC = [3:0]
PORT fpga_0_ethernet_0_PHY_col_pin = fpga_0_ethernet_0_PHY_col, DIR = I
PORT fpga_0_ethernet_0_PHY_rx_er_pin = fpga_0_ethernet_0_PHY_rx_er, DIR = I
PORT fpga_0_ethernet_0_PHY_tx_en_pin = fpga_0_ethernet_0_PHY_tx_en, DIR = O
PORT fpga_0_ethernet_0_PHY_tx_data_pin = fpga_0_ethernet_0_PHY_tx_data, DIR = O, VEC = [3:0]
PORT fpga_0_ethernet_0_PHY_Mii_clk_pin = fpga_0_ethernet_0_PHY_Mii_clk, DIR = IO
PORT fpga_0_ethernet_0_PHY_Mii_data_pin = fpga_0_ethernet_0_PHY_Mii_data, DIR = IO
PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RST
PORT fpga_0_ethernet_0_PHY_tx_er_pin = fpga_0_ethernet_0_PHY_tx_er, DIR = O
PORT fpga_0_ethernet_0_PHY_rst_n_pin = fpga_0_ethernet_0_PHY_rst_n, DIR = O
PORT fpga_0_sdram_1_SDRAM_Clk_pin = fpga_0_sdram_1_SDRAM_Clk, DIR = O
PORT fpga_0_sdram_1_SDRAM_CKE_pin = fpga_0_sdram_1_SDRAM_CKE, DIR = O
PORT fpga_0_sdram_1_SDRAM_CSn_pin = fpga_0_sdram_1_SDRAM_CSn, DIR = O
PORT fpga_0_sdram_1_SDRAM_RASn_pin = fpga_0_sdram_1_SDRAM_RASn, DIR = O
PORT fpga_0_sdram_1_SDRAM_CASn_pin = fpga_0_sdram_1_SDRAM_CASn, DIR = O
PORT fpga_0_sdram_1_SDRAM_WEn_pin = fpga_0_sdram_1_SDRAM_WEn, DIR = O
PORT fpga_0_sdram_1_SDRAM_DQM_pin = fpga_0_sdram_1_SDRAM_DQM, DIR = O, VEC = [0:3]
PORT fpga_0_sdram_1_SDRAM_BankAddr_pin = fpga_0_sdram_1_SDRAM_BankAddr, DIR = O, VEC = [0:1]
PORT fpga_0_sdram_1_SDRAM_Addr_pin = fpga_0_sdram_1_SDRAM_Addr, DIR = O, VEC = [0:12]
PORT fpga_0_sdram_1_SDRAM_DQ_pin = fpga_0_sdram_1_SDRAM_DQ, DIR = IO, VEC = [0:31]
PORT fpga_0_sdram_1_SDRAM_Init_done_pin = fpga_0_sdram_1_SDRAM_Init_done, DIR = O
PORT fpga_0_ethernet_1_PHY_tx_clk_pin = fpga_0_ethernet_1_PHY_tx_clk, DIR = I
PORT fpga_0_ethernet_1_PHY_rx_clk_pin = fpga_0_ethernet_1_PHY_rx_clk, DIR = I
PORT fpga_0_ethernet_1_PHY_crs_pin = fpga_0_ethernet_1_PHY_crs, DIR = I
PORT fpga_0_ethernet_1_PHY_dv_pin = fpga_0_ethernet_1_PHY_dv, DIR = I
PORT fpga_0_ethernet_1_PHY_rx_data_pin = fpga_0_ethernet_1_PHY_rx_data, DIR = I, VEC = [3:0]
PORT fpga_0_ethernet_1_PHY_col_pin = fpga_0_ethernet_1_PHY_col, DIR = I
PORT fpga_0_ethernet_1_PHY_rx_er_pin = fpga_0_ethernet_1_PHY_rx_er, DIR = I
PORT fpga_0_ethernet_1_PHY_Mii_clk_pin = fpga_0_ethernet_1_PHY_Mii_clk, DIR = IO
PORT fpga_0_ethernet_1_PHY_tx_en_pin = fpga_0_ethernet_1_PHY_tx_en, DIR = O
PORT fpga_0_ethernet_1_PHY_tx_data_pin = fpga_0_ethernet_1_PHY_tx_data, DIR = O, VEC = [3:0]
PORT fpga_0_ethernet_1_PHY_rst_n_pin = fpga_0_ethernet_1_PHY_rst_n, DIR = O
PORT fpga_0_ethernet_1_PHY_Mii_data_pin = fpga_0_ethernet_1_PHY_Mii_data, DIR = IO
PORT fpga_0_ethernet_1_PHY_tx_er_pin = fpga_0_ethernet_1_PHY_tx_er, DIR = O
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 5.00.c
PARAMETER C_USE_FPU = 0
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_NUMBER_OF_PC_BRK = 2
PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 0
PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 0
BUS_INTERFACE DLMB = dlmb_0
BUS_INTERFACE ILMB = ilmb_0
BUS_INTERFACE DOPB = mb_opb_0
BUS_INTERFACE IOPB = mb_opb_0
PORT DBG_CAPTURE = DBG_CAPTURE_s
PORT DBG_CLK = DBG_CLK_s
PORT DBG_REG_EN = DBG_REG_EN_s
PORT DBG_TDI = DBG_TDI_s
PORT DBG_TDO = DBG_TDO_s
PORT DBG_UPDATE = DBG_UPDATE_s
PORT Interrupt = Interrupt_0
END
BEGIN opb_v20
PARAMETER INSTANCE = mb_opb_0
PARAMETER HW_VER = 1.10.c
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_rst_s
PORT OPB_Clk = sys_clk_s
END
BEGIN opb_mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 2.00.a
PARAMETER C_MB_DBG_PORTS = 2
PARAMETER C_USE_UART = 0
PARAMETER C_BASEADDR = 0x41400000
PARAMETER C_HIGHADDR = 0x4140FFFF
BUS_INTERFACE SOPB = mb_opb_0
PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
PORT DBG_CLK_0 = DBG_CLK_s
PORT DBG_REG_EN_0 = DBG_REG_EN_s
PORT DBG_TDI_0 = DBG_TDI_s
PORT DBG_TDO_0 = DBG_TDO_s
PORT DBG_UPDATE_0 = DBG_UPDATE_s
PORT Dbg_Clk_1 = microblaze_1_Dbg_Clk
PORT Dbg_TDI_1 = microblaze_1_Dbg_TDI
PORT Dbg_TDO_1 = microblaze_1_Dbg_TDO
PORT Dbg_Reg_En_1 = microblaze_1_Dbg_Reg_En
PORT Dbg_Capture_1 = microblaze_1_Dbg_Capture
PORT Dbg_Update_1 = microblaze_1_Dbg_Update
END
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END
BEGIN lmb_v10
PARAMETER INSTANCE = dlmb_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr_0
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00003FFF
BUS_INTERFACE SLMB = dlmb_0
BUS_INTERFACE BRAM_PORT = dlmb_port
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr_0
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00003FFF
BUS_INTERFACE SLMB = ilmb_0
BUS_INTERFACE BRAM_PORT = ilmb_port
END
BEGIN bram_block
PARAMETER INSTANCE = lmb_bram_0
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END
BEGIN opb_uartlite
PARAMETER INSTANCE = RS232_0
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 57600
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_CLK_FREQ = 100000000
PARAMETER C_BASEADDR = 0x40600000
PARAMETER C_HIGHADDR = 0x4060FFFF
BUS_INTERFACE SOPB = mb_opb_0
PORT Interrupt = RS232_0_Interrupt
PORT RX = fpga_0_RS232_0_RX
PORT TX = fpga_0_RS232_0_TX
END
BEGIN opb_gpio
PARAMETER INSTANCE = LEDs
PARAMETER HW_VER = 3.01.b
PARAMETER C_GPIO_WIDTH = 8
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_BASEADDR = 0x40000000
PARAMETER C_HIGHADDR = 0x4000FFFF
BUS_INTERFACE SOPB = mb_opb_0
PORT GPIO_IO = fpga_0_LEDs_GPIO_IO
END
BEGIN opb_gpio
PARAMETER INSTANCE = Push_Button_SW4
PARAMETER HW_VER = 3.01.b
PARAMETER C_GPIO_WIDTH = 1
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_BASEADDR = 0x40020000
PARAMETER C_HIGHADDR = 0x4002FFFF
BUS_INTERFACE SOPB = mb_opb_0
PORT GPIO_in = fpga_0_Push_Button_SW4_GPIO_in
END
BEGIN opb_gpio
PARAMETER INSTANCE = DIP_Switches
PARAMETER HW_VER = 3.01.b
PARAMETER C_GPIO_WIDTH = 8
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_BASEADDR = 0x40040000
PARAMETER C_HIGHADDR = 0x4004FFFF
BUS_INTERFACE SOPB = mb_opb_0
PORT GPIO_in = fpga_0_DIP_Switches_GPIO_in
END
BEGIN opb_ddr
PARAMETER INSTANCE = sdram_0
PARAMETER HW_VER = 2.00.c
PARAMETER C_OPB_CLK_PERIOD_PS = 10000
PARAMETER C_REG_DIMM = 0
PARAMETER C_DDR_TMRD = 15000
PARAMETER C_DDR_TWR = 15000
PARAMETER C_DDR_TWTR = 1
PARAMETER C_DDR_TRAS = 42000
PARAMETER C_DDR_TRC = 65000
PARAMETER C_DDR_TRFC = 75000
PARAMETER C_DDR_TRCD = 20000
PARAMETER C_DDR_TRRD = 15000
PARAMETER C_DDR_TRP = 20000
PARAMETER C_DDR_TREFC = 70300000
PARAMETER C_DDR_TREFI = 7800000
PARAMETER C_DDR_DWIDTH = 16
PARAMETER C_DDR_AWIDTH = 13
PARAMETER C_DDR_COL_AWIDTH = 9
PARAMETER C_DDR_BANK_AWIDTH = 2
PARAMETER C_NUM_CLK_PAIRS = 2
PARAMETER C_MEM0_BASEADDR = 0x24000000
PARAMETER C_MEM0_HIGHADDR = 0x25FFFFFF
BUS_INTERFACE SOPB = mb_opb_0
PORT DDR_Clk = fpga_0_sdram_0_DDR_Clk
PORT DDR_Clkn = fpga_0_sdram_0_DDR_Clkn
PORT DDR_Addr = fpga_0_sdram_0_DDR_Addr
PORT DDR_BankAddr = fpga_0_sdram_0_DDR_BankAddr
PORT DDR_CASn = fpga_0_sdram_0_DDR_CASn
PORT DDR_CKE = fpga_0_sdram_0_DDR_CKE
PORT DDR_CSn = fpga_0_sdram_0_DDR_CSn
PORT DDR_RASn = fpga_0_sdram_0_DDR_RASn
PORT DDR_WEn = fpga_0_sdram_0_DDR_WEn
PORT DDR_DM = fpga_0_sdram_0_DDR_DM
PORT DDR_DQS = fpga_0_sdram_0_DDR_DQS
PORT DDR_DQ = fpga_0_sdram_0_DDR_DQ
PORT Device_Clk90_in = clk_90_s
PORT Device_Clk90_in_n = clk_90_n_s
PORT Device_Clk = sys_clk_s
PORT Device_Clk_n = sys_clk_n_s
PORT DDR_Clk90_in = ddr_clk_90_s
PORT DDR_Clk90_in_n = ddr_clk_90_n_s
END
BEGIN opb_emc
PARAMETER INSTANCE = FLASH_4Mx16
PARAMETER HW_VER = 2.00.a
PARAMETER C_OPB_CLK_PERIOD_PS = 10000
PARAMETER C_NUM_BANKS_MEM = 1
PARAMETER C_MAX_MEM_WIDTH = 16
PARAMETER C_MEM0_WIDTH = 16
PARAMETER C_TCEDV_PS_MEM_0 = 120000
PARAMETER C_TWC_PS_MEM_0 = 120000
PARAMETER C_TAVDV_PS_MEM_0 = 120000
PARAMETER C_TWP_PS_MEM_0 = 120000
PARAMETER C_THZCE_PS_MEM_0 = 35000
PARAMETER C_TLZWE_PS_MEM_0 = 35000
PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 0
PARAMETER C_MEM0_BASEADDR = 0x26000000
PARAMETER C_MEM0_HIGHADDR = 0x267FFFFF
BUS_INTERFACE SOPB = mb_opb_0
PORT Mem_A = fpga_0_FLASH_4Mx16_Mem_A_split
PORT Mem_DQ = fpga_0_FLASH_4Mx16_Mem_DQ
PORT Mem_WEN = fpga_0_FLASH_4Mx16_Mem_WEN
PORT Mem_OEN = fpga_0_FLASH_4Mx16_Mem_OEN
PORT Mem_CEN = fpga_0_FLASH_4Mx16_Mem_CEN
PORT Mem_RPN = fpga_0_FLASH_4Mx16_Mem_RPN
END
BEGIN opb_ethernet
PARAMETER INSTANCE = ethernet_0
PARAMETER HW_VER = 1.04.a
PARAMETER C_DMA_PRESENT = 1
PARAMETER C_IPIF_RDFIFO_DEPTH = 65536
PARAMETER C_IPIF_WRFIFO_DEPTH = 65536
PARAMETER C_OPB_CLK_PERIOD_PS = 10000
PARAMETER C_BASEADDR = 0x40C00000
PARAMETER C_HIGHADDR = 0x40C0FFFF
BUS_INTERFACE SOPB = mb_opb_0
PORT IP2INTC_Irpt = ethernet_0_IP2INTC_Irpt
PORT PHY_tx_clk = fpga_0_ethernet_0_PHY_tx_clk
PORT PHY_rx_clk = fpga_0_ethernet_0_PHY_rx_clk
PORT PHY_crs = fpga_0_ethernet_0_PHY_crs
PORT PHY_dv = fpga_0_ethernet_0_PHY_dv
PORT PHY_rx_data = fpga_0_ethernet_0_PHY_rx_data
PORT PHY_col = fpga_0_ethernet_0_PHY_col
PORT PHY_rx_er = fpga_0_ethernet_0_PHY_rx_er
PORT PHY_tx_en = fpga_0_ethernet_0_PHY_tx_en
PORT PHY_tx_data = fpga_0_ethernet_0_PHY_tx_data
PORT PHY_Mii_clk = fpga_0_ethernet_0_PHY_Mii_clk
PORT PHY_Mii_data = fpga_0_ethernet_0_PHY_Mii_data
PORT PHY_tx_er = fpga_0_ethernet_0_PHY_tx_er
PORT PHY_rst_n = fpga_0_ethernet_0_PHY_rst_n
END
BEGIN opb_timer
PARAMETER INSTANCE = timer_0
PARAMETER HW_VER = 1.00.b
PARAMETER C_COUNT_WIDTH = 32
PARAMETER C_ONE_TIMER_ONLY = 1
PARAMETER C_BASEADDR = 0x41C00000
PARAMETER C_HIGHADDR = 0x41C0FFFF
BUS_INTERFACE SOPB = mb_opb_0
PORT Interrupt = timer_0_Interrupt
END
BEGIN opb_intc
PARAMETER INSTANCE = intc_0
PARAMETER HW_VER = 1.00.c
PARAMETER C_BASEADDR = 0x41200000
PARAMETER C_HIGHADDR = 0x4120FFFF
BUS_INTERFACE SOPB = mb_opb_0
PORT Irq = Interrupt_0
PORT Intr = RS232_0_Interruptðernet_0_IP2INTC_Irpt&timer_0_Interrupt
END
BEGIN util_bus_split
PARAMETER INSTANCE = FLASH_4Mx16_util_bus_split_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE_IN = 32
PARAMETER C_LEFT_POS = 9
PARAMETER C_SPLIT = 31
PORT Sig = fpga_0_FLASH_4Mx16_Mem_A_split
PORT Out1 = fpga_0_FLASH_4Mx16_Mem_A
END
BEGIN util_vector_logic
PARAMETER INSTANCE = sysclk_inv
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE = 1
PARAMETER C_OPERATION = not
PORT Op1 = sys_clk_s
PORT Res = sys_clk_n_s
END
BEGIN util_vector_logic
PARAMETER INSTANCE = clk90_inv
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE = 1
PARAMETER C_OPERATION = not
PORT Op1 = clk_90_s
PORT Res = clk_90_n_s
END
BEGIN util_vector_logic
PARAMETER INSTANCE = ddr_clk90_inv
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE = 1
PARAMETER C_OPERATION = not
PORT Op1 = ddr_clk_90_s
PORT Res = ddr_clk_90_n_s
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLK90_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_DLL_FREQUENCY_MODE = LOW
PARAMETER C_EXT_RESET_HIGH = 1
PORT CLKIN = dcm_clk_s
PORT CLK0 = sys_clk_s
PORT CLK90 = clk_90_s
PORT CLKFB = sys_clk_s
PORT RST = net_gnd
PORT LOCKED = dcm_0_lock
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLK90_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_DLL_FREQUENCY_MODE = LOW
PARAMETER C_PHASE_SHIFT = 110
PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED
PARAMETER C_EXT_RESET_HIGH = 0
PORT CLKIN = ddr_feedback_s
PORT CLK90 = ddr_clk_90_s
PORT CLK0 = dcm_1_FB
PORT CLKFB = dcm_1_FB
PORT RST = dcm_0_lock
PORT LOCKED = dcm_1_lock
END
BEGIN microblaze
PARAMETER INSTANCE = microblaze_1
PARAMETER HW_VER = 5.00.c
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_NUMBER_OF_PC_BRK = 2
PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 0
PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 0
BUS_INTERFACE DOPB = mb_opb_1
BUS_INTERFACE IOPB = mb_opb_1
BUS_INTERFACE DLMB = dlmb_1
BUS_INTERFACE ILMB = ilmb_1
PORT Dbg_Clk = microblaze_1_Dbg_Clk
PORT Dbg_TDI = microblaze_1_Dbg_TDI
PORT Dbg_TDO = microblaze_1_Dbg_TDO
PORT Dbg_Reg_En = microblaze_1_Dbg_Reg_En
PORT Dbg_Capture = microblaze_1_Dbg_Capture
PORT Dbg_Update = microblaze_1_Dbg_Update
PORT INTERRUPT = Interrupt_1
END
BEGIN opb_v20
PARAMETER INSTANCE = mb_opb_1
PARAMETER HW_VER = 1.10.c
PORT OPB_Clk = sys_clk_s
PORT SYS_Rst = sys_rst_s
END
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb_1
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk_s
PORT SYS_Rst = sys_rst_s
END
BEGIN lmb_v10
PARAMETER INSTANCE = dlmb_1
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk_s
PORT SYS_Rst = sys_rst_s
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr_1
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00003FFF
BUS_INTERFACE SLMB = dlmb_1
BUS_INTERFACE BRAM_PORT = dlmb_cntlr_1_BRAM_PORT
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr_1
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00003FFF
BUS_INTERFACE SLMB = ilmb_1
BUS_INTERFACE BRAM_PORT = ilmb_cntlr_1_BRAM_PORT
END
BEGIN opb_uartlite
PARAMETER INSTANCE = RS232_1
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 57600
PARAMETER C_USE_PARITY = 0
PARAMETER C_ODD_PARITY = 0
PARAMETER C_CLK_FREQ = 100000000
PARAMETER C_BASEADDR = 0x40600000
PARAMETER C_HIGHADDR = 0x4060FFFF
BUS_INTERFACE SOPB = mb_opb_1
PORT Interrupt = RS232_1_Interrupt
END
BEGIN bram_block
PARAMETER INSTANCE = lmb_bram_1
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_cntlr_1_BRAM_PORT
BUS_INTERFACE PORTB = dlmb_cntlr_1_BRAM_PORT
END
BEGIN opb_sdram
PARAMETER INSTANCE = sdram_1
PARAMETER HW_VER = 1.00.e
PARAMETER C_BASEADDR = 0x24000000
PARAMETER C_HIGHADDR = 0x25FFFFFF
PARAMETER C_INCLUDE_BURST_SUPPORT = 0
PARAMETER C_INCLUDE_HIGHSPEED_PIPE = 0
PARAMETER C_SDRAM_COL_AWIDTH = 9
PARAMETER C_SDRAM_TRAS = 44000
PARAMETER C_SDRAM_TRC = 66000
PARAMETER C_SDRAM_TRFC = 66000
BUS_INTERFACE SOPB = mb_opb_1
PORT SDRAM_Clk = fpga_0_sdram_1_SDRAM_Clk
PORT SDRAM_CKE = fpga_0_sdram_1_SDRAM_CKE
PORT SDRAM_CSn = fpga_0_sdram_1_SDRAM_CSn
PORT SDRAM_RASn = fpga_0_sdram_1_SDRAM_RASn
PORT SDRAM_CASn = fpga_0_sdram_1_SDRAM_CASn
PORT SDRAM_WEn = fpga_0_sdram_1_SDRAM_WEn
PORT SDRAM_DQM = fpga_0_sdram_1_SDRAM_DQM
PORT SDRAM_BankAddr = fpga_0_sdram_1_SDRAM_BankAddr
PORT SDRAM_Addr = fpga_0_sdram_1_SDRAM_Addr
PORT SDRAM_DQ = fpga_0_sdram_1_SDRAM_DQ
PORT SDRAM_Init_done = fpga_0_sdram_1_SDRAM_Init_done
PORT SDRAM_Clk_in = sys_clk_s
END
BEGIN opb_ethernet
PARAMETER INSTANCE = ethernet_1
PARAMETER HW_VER = 1.04.a
PARAMETER C_DMA_PRESENT = 1
PARAMETER C_IPIF_RDFIFO_DEPTH = 65536
PARAMETER C_IPIF_WRFIFO_DEPTH = 65536
PARAMETER C_BASEADDR = 0x40C00000
PARAMETER C_HIGHADDR = 0x40C0FFFF
BUS_INTERFACE SOPB = mb_opb_1
PORT PHY_rx_er = fpga_0_ethernet_1_PHY_rx_er
PORT PHY_col = fpga_0_ethernet_1_PHY_col
PORT PHY_rx_data = fpga_0_ethernet_1_PHY_rx_data
PORT PHY_dv = fpga_0_ethernet_1_PHY_dv
PORT PHY_crs = fpga_0_ethernet_1_PHY_crs
PORT PHY_rx_clk = fpga_0_ethernet_1_PHY_rx_clk
PORT PHY_tx_clk = fpga_0_ethernet_1_PHY_tx_clk
PORT PHY_Mii_clk = fpga_0_ethernet_1_PHY_Mii_clk
PORT PHY_tx_en = fpga_0_ethernet_1_PHY_tx_en
PORT PHY_tx_data = fpga_0_ethernet_1_PHY_tx_data
PORT PHY_rst_n = fpga_0_ethernet_1_PHY_rst_n
PORT PHY_Mii_data = fpga_0_ethernet_1_PHY_Mii_data
PORT IP2INTC_Irpt = ethernet_1_IP2INTC_Irpt
PORT PHY_tx_er = fpga_0_ethernet_1_PHY_tx_er
END
BEGIN opb_timer
PARAMETER INSTANCE = timer_1
PARAMETER HW_VER = 1.00.b
PARAMETER C_ONE_TIMER_ONLY = 1
PARAMETER C_BASEADDR = 0x41C00000
PARAMETER C_HIGHADDR = 0x41C0FFFF
BUS_INTERFACE SOPB = mb_opb_1
PORT Interrupt = timer_1_Interrupt
END
BEGIN opb_intc
PARAMETER INSTANCE = intc_1
PARAMETER HW_VER = 1.00.c
PARAMETER C_BASEADDR = 0x41200000
PARAMETER C_HIGHADDR = 0x4120FFFF
BUS_INTERFACE SOPB = mb_opb_1
PORT Intr = RS232_1_Interruptðernet_1_IP2INTC_Irpt&timer_1_Interrupt
PORT Irq = Interrupt_1
END
BEGIN opb_gpio
PARAMETER INSTANCE = gpio_1
PARAMETER HW_VER = 3.01.b
PARAMETER C_BASEADDR = 0x40000000
PARAMETER C_HIGHADDR = 0x4000FFFF
BUS_INTERFACE SOPB = mb_opb_1
END
PARAMETER VERSION = 2.2.0
BEGIN OS
PARAMETER OS_NAME = uclinux
PARAMETER OS_VER = 1.00.d
PARAMETER PROC_INSTANCE = microblaze_0
PARAMETER lmb_memory = dlmb_cntlr_0
PARAMETER main_memory_bank = 0
PARAMETER main_memory = sdram_0
PARAMETER stdin = RS232_0
PARAMETER stdout = RS232_0
PARAMETER TARGET_DIR = ./linux
END
BEGIN OS
PARAMETER OS_NAME = uclinux
PARAMETER OS_VER = 1.00.d
PARAMETER PROC_INSTANCE = microblaze_1
PARAMETER lmb_memory = dlmb_cntlr_1
PARAMETER main_memory_bank = 0
PARAMETER main_memory = sdram_1
PARAMETER stdin = RS232_1
PARAMETER stdout = RS232_1
PARAMETER TARGET_DIR = ./linux
END
BEGIN PROCESSOR
PARAMETER DRIVER_NAME = cpu
PARAMETER DRIVER_VER = 1.01.a
PARAMETER HW_INSTANCE = microblaze_0
PARAMETER COMPILER = mb-gcc
PARAMETER ARCHIVER = mb-ar
PARAMETER XMDSTUB_PERIPHERAL = debug_module
END
BEGIN PROCESSOR
PARAMETER DRIVER_NAME = cpu
PARAMETER DRIVER_VER = 1.01.a
PARAMETER HW_INSTANCE = microblaze_1
PARAMETER COMPILER = mb-gcc
PARAMETER ARCHIVER = mb-ar
PARAMETER xmdstub_peripheral = debug_module
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = opbarb
PARAMETER DRIVER_VER = 1.02.a
PARAMETER HW_INSTANCE = mb_opb_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 1.01.a
PARAMETER HW_INSTANCE = debug_module
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = dlmb_cntlr_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ilmb_cntlr_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 1.01.a
PARAMETER HW_INSTANCE = RS232_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpio
PARAMETER DRIVER_VER = 2.01.a
PARAMETER HW_INSTANCE = LEDs
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpio
PARAMETER DRIVER_VER = 2.01.a
PARAMETER HW_INSTANCE = Push_Button_SW4
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpio
PARAMETER DRIVER_VER = 2.01.a
PARAMETER HW_INSTANCE = DIP_Switches
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = sdram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = sdram_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = emc
PARAMETER DRIVER_VER = 2.00.a
PARAMETER HW_INSTANCE = FLASH_4Mx16
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = emac
PARAMETER DRIVER_VER = 1.01.a
PARAMETER HW_INSTANCE = ethernet_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = tmrctr
PARAMETER DRIVER_VER = 1.00.b
PARAMETER HW_INSTANCE = timer_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = intc
PARAMETER DRIVER_VER = 1.00.c
PARAMETER HW_INSTANCE = intc_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = opbarb
PARAMETER DRIVER_VER = 1.02.a
PARAMETER HW_INSTANCE = mb_opb_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = dlmb_cntlr_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ilmb_cntlr_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 1.01.a
PARAMETER HW_INSTANCE = RS232_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = sdram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = sdram_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = emac
PARAMETER DRIVER_VER = 1.01.a
PARAMETER HW_INSTANCE = ethernet_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = tmrctr
PARAMETER DRIVER_VER = 1.00.b
PARAMETER HW_INSTANCE = timer_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = intc
PARAMETER DRIVER_VER = 1.00.c
PARAMETER HW_INSTANCE = intc_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpio
PARAMETER DRIVER_VER = 2.01.a
PARAMETER HW_INSTANCE = gpio_1
END