Re: [microblaze-uclinux] EDK 9.1 - DDR General question

[John Williams <jwilliams@xxxxxxxxxxxxxx>]

Hi Cedric,

Cedric LORANT wrote:
> Hi everybody,
>
> This probably not the right group where I should ask this, but may be
> someone already had the same problem within the ?CLinux community.
>
> I am experiencing a strange problem with a DDR chip (Micro 46V32M16 - the
> same a the one used on SP3E500 and SP3E1600 Xilinx kit - same speed grade).
> I use the same DDR parameters as the one used on the demo boards.
> NOTE: It is a custom designed board.

Do you have the DDR clock feedback trace on the board, and is it coming 
back into the DDR clocking structure within the EDK project?

> Using the Memory Test application from EDK build:
> The problem is that it passes the 32 bits memory test and also the 16 bits
> memory test, but not the 8 bits.
> When I am writing by hand 16 bits or 32 bits value, it fully works, but when
> I do it in Byte format, some bits are badly written into memory.
>
> Example :
>
> Write		Read
> 0x1234		0x1234		Ok
> 0x0008		0x0808		Bad
> 0x0009		0x0809		Bad
> 0x0708		0x0F08		Bad
> 0x1122		0x1132		Bad
> 0x0007		0x0006		Bad
> 0xaa55		0xa245		Bad

Examine these patterns in binary - check for stuck bits etc.  Is the 
order of the writes/reads important?

Which memory controller are you using - mch_opb_ddr, or the older opb_ddr?

Regards,

John
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