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RE: [microblaze-uclinux] Problem loading U-boot

To: <microblaze-uclinux@xxxxxxxxxxxxxx>
Subject: RE: [microblaze-uclinux] Problem loading U-boot
From: <ext.Daniel.Persson@xxxxxxxxxxxxxxx>
Date: Thu, 20 Sep 2007 15:57:09 +0200
In-reply-to: <46F26255.7000104@xxxxxxxxxxxxxx>
References: <B28B13F99A32824C90752FFF38BAEF6B42E412@xxxxxxxxxxxxxxxxxxxxx> <46F26255.7000104@xxxxxxxxxxxxxx>
Reply-to: microblaze-uclinux@xxxxxxxxxxxxxx
Sender: owner-microblaze-uclinux@xxxxxxxxxxxxxx
Thread-index: Acf7il6MsXAxanCfTGOs+HculRKuEAAAG4og
Thread-topic: [microblaze-uclinux] Problem loading U-boot
 Hi Benny,
I know its hard to really help without a board testing it on. But I'll
try to explain what I found.

At first I thought the problem where in the DDR memory, as the output
stops executing in the middle of the init for the SDRAM. However
(correct me if I'm wrong) I think the problem lays with the flash
memory. I looked through the board.c file and I figure that the UART
output is a bit behind what the processor acually does. So what I'm
thinking is if the UART is behind then the init of the flash is more
likely whats cusing the problem.

This makes sence as I haven't been able to test the flash from EDK. I
have been searching around abit for an test application that I can run
for testing the flash read/write. However I cant find one.

The flash memory is 2x Toshiba multi-chip SDRAM and flash combined
chips. They are togheter implented on 32bit data bus. When this board
where made its routed as an Memec P160 communication module. I found the
.xbd files for this board and uses the same parameters. I tested the
SDRAM part with no problem using the XPS autogenerated memory test
application. So I figured that the flash part should also be working.
The chips are according to the datasheet compatible with CFI standard.

Does anyone know an easy way to test the flash write/read ability?

Might the problem be that I have to enable some other driver for this
flash when generating u-boot? Or should it be compatible?

Thanks in advance,
Daniel

-----Original Message-----
From: owner-microblaze-uclinux@xxxxxxxxxxxxxx
[mailto:owner-microblaze-uclinux@xxxxxxxxxxxxxx] On Behalf Of Benny Chen
Sent: den 20 september 2007 14:07
To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: Re: [microblaze-uclinux] Problem loading U-boot

Hi Daniel,
It is hard to debug without a board.  But from your log it seems that
you get a reboot during the U-Boot board init time.  Particularly during
the initialization of the GBL data structure "gd" (have a look at
lib_microblaze/board.c).  Probably related to writing to the wrong part
of system memory.  Good chance that it is related to your U-Boot build.

Not much that I can tell you.

Cheers,
Benny


ext.Daniel.Persson@xxxxxxxxxxxxxxx wrote:
> Hi,
>  
> I'm trying to get petalinux run on a custom made board. On the board 
> there is an Virtex II Pro, DDR, flash and ethernet.
>  
> The problem is when I've downloaded the u-boot.srec file to the board 
> as you can see below
>  
>  
> FS-BOOT: Image download successful.
> FS-BOOT: Warning image location differ from default boot location. 
> Image will no
> t boot automatically after POR.
> FS-BOOT: Press 'n' to boot old image.
> FS-BOOT: Use new image.
> FS-BOOT: Booting image...
> SDRAM :
> Enabling caches...Icache:OK...Dcache:OK
>         U-Boot Start:0x23fc0000
>         Malloc Start:0x23f80000
>         Board Info Start:0x23f7ffd0
>         Boot Parameters Start:0x23
> =================================================
> FS-BOOT First Stage Bootloader (c) 2006 PetaLogix 
> =================================================
> FS-BOOT: System initialisation completed.
> FS-BOOT: No existing image in FLASH.  Starting image download.
> FS-BOOT: Waiting for SREC image....
>  
>  
> I cant figure out why the system just suddenly reboots when it comes 
> to the "Boot Parameters Start:0x23" line. This line shouldn't be just
> 0x23 as the memory is mapped from 0x22000000 to 0x24000000.
>  
> I'm using kernel 2.4 and I have successfully built a working system on

> my Spartan 3E starter kit, using the same method.
>  
> I would be very happy if someone could help me, or atleast point me 
> into the right direction where I should look.
>  
> Thank you in advance
> //Daniel
>  
> Here below I also paste the auto-config.in file
>  
>
> ############################################################
>
> #
>
> # CAUTION: This file is automatically generated by libgen.
>
> # EDK Version: Xilinx EDK 8.1.02 EDK_I.20.4
>
> # Description: PetaLinux Configuration File - Kernel Version 2.4.x
>
> #
>
> ############################################################
>
>  
>
> # MAIN_MEMORY Settings
>
> define_hex CONFIG_XILINX_ERAM_START 0x22000000
>
> define_hex CONFIG_XILINX_ERAM_SIZE 0x02000000
>
> # FLASH_MEMORY Settings
>
> define_hex CONFIG_XILINX_FLASH_START 0x21000000
>
> define_hex CONFIG_XILINX_FLASH_SIZE 0x00800000
>
> define_int CONFIG_XILINX_FLASH_WIDTH 32
>
> define_int CONFIG_XILINX_FLASH_DATAWIDTH_MATCHING 0
>
> # LMB_MEMORY Settings
>
> define_hex CONFIG_XILINX_LMB_START 0x00000000
>
> define_hex CONFIG_XILINX_LMB_SIZE 0x00002000
>
> # System Clock Frequency
>
> define_int CONFIG_XILINX_CPU_CLOCK_FREQ 92160000
>
> # Definitions for MICROBLAZE0
>
> define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
>
> define_string CONFIG_XILINX_MICROBLAZE0_FAMILY virtex2p
>
> define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
>
> define_int CONFIG_XILINX_MICROBLAZE0_D_OPB 1
>
> define_int CONFIG_XILINX_MICROBLAZE0_D_LMB 1
>
> define_int CONFIG_XILINX_MICROBLAZE0_I_OPB 1
>
> define_int CONFIG_XILINX_MICROBLAZE0_I_LMB 1
>
> define_int CONFIG_XILINX_MICROBLAZE0_USE_BARREL 0
>
> define_int CONFIG_XILINX_MICROBLAZE0_USE_DIV 0
>
> define_int CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL 1
>
> define_int CONFIG_XILINX_MICROBLAZE0_USE_FPU 0
>
> define_int CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR 0
>
> define_int CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR 0
>
> define_int CONFIG_XILINX_MICROBLAZE0_UNALIGNED_EXCEPTIONS 0
>
> define_int CONFIG_XILINX_MICROBLAZE0_ILL_OPCODE_EXCEPTION 0
>
> define_int CONFIG_XILINX_MICROBLAZE0_IOPB_BUS_EXCEPTION 0
>
> define_int CONFIG_XILINX_MICROBLAZE0_DOPB_BUS_EXCEPTION 0
>
> define_int CONFIG_XILINX_MICROBLAZE0_DIV_ZERO_EXCEPTION 0
>
> define_int CONFIG_XILINX_MICROBLAZE0_FPU_EXCEPTION 0
>
> define_int CONFIG_XILINX_MICROBLAZE0_DEBUG_ENABLED 1
>
> define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_PC_BRK 2
>
> define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_RD_ADDR_BRK 0
>
> define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_WR_ADDR_BRK 0
>
> define_int CONFIG_XILINX_MICROBLAZE0_INTERRUPT_IS_EDGE 0
>
> define_int CONFIG_XILINX_MICROBLAZE0_EDGE_IS_POSITIVE 1
>
> define_int CONFIG_XILINX_MICROBLAZE0_FSL_LINKS 1
>
> define_int CONFIG_XILINX_MICROBLAZE0_FSL_DATA_SIZE 32
>
> define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_BASEADDR 0x22000000
>
> define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_HIGHADDR 0x23FFFFFF
>
> define_int CONFIG_XILINX_MICROBLAZE0_USE_ICACHE 1
>
> define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_ICACHE_WR 1
>
> define_int CONFIG_XILINX_MICROBLAZE0_ADDR_TAG_BITS 12
>
> define_int CONFIG_XILINX_MICROBLAZE0_CACHE_BYTE_SIZE 8192
>
> define_int CONFIG_XILINX_MICROBLAZE0_ICACHE_USE_FSL 1
>
> define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_BASEADDR 0x22000000
>
> define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_HIGHADDR 0x23FFFFFF
>
> define_int CONFIG_XILINX_MICROBLAZE0_USE_DCACHE 1
>
> define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_DCACHE_WR 1
>
> define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_ADDR_TAG 12
>
> define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_BYTE_SIZE 8192
>
> define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_USE_FSL 1
>
> define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
>
> define_string CONFIG_XILINX_MICROBLAZE0_HW_VER 4.00.a
>
> # Definitions for LMB_BRAM_IF_CNTLR_0
>
> define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE dlmb_cntlr
>
> define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_BASEADDR 0x00000000
>
> define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HIGHADDR 0x00001FFF
>
> define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_MASK 0x03400000
>
> define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_AWIDTH 32
>
> define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_DWIDTH 32
>
> define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE dlmb_cntlr
>
> define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HW_VER 1.00.b
>
> # Definitions for LMB_BRAM_IF_CNTLR_1
>
> define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE ilmb_cntlr
>
> define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_BASEADDR 0x00000000
>
> define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HIGHADDR 0x00001FFF
>
> define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_MASK 0x03400000
>
> define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_AWIDTH 32
>
> define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_DWIDTH 32
>
> define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE ilmb_cntlr
>
> define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HW_VER 1.00.b
>
> # Definitions for V20_0
>
> define_string CONFIG_XILINX_V20_0_INSTANCE mb_opb
>
> define_hex CONFIG_XILINX_V20_0_BASEADDR 0xFFFFFFFF
>
> define_hex CONFIG_XILINX_V20_0_HIGHADDR 0x00000000
>
> define_int CONFIG_XILINX_V20_0_OPB_AWIDTH 32
>
> define_int CONFIG_XILINX_V20_0_OPB_DWIDTH 32
>
> define_int CONFIG_XILINX_V20_0_NUM_MASTERS 2
>
> define_int CONFIG_XILINX_V20_0_NUM_SLAVES 7
>
> define_int CONFIG_XILINX_V20_0_USE_LUT_OR 1
>
> define_int CONFIG_XILINX_V20_0_EXT_RESET_HIGH 0
>
> define_int CONFIG_XILINX_V20_0_DYNAM_PRIORITY 0
>
> define_int CONFIG_XILINX_V20_0_PARK 0
>
> define_int CONFIG_XILINX_V20_0_PROC_INTRFCE 0
>
> define_int CONFIG_XILINX_V20_0_REG_GRANTS 1
>
> define_int CONFIG_XILINX_V20_0_DEV_BLK_ID 0
>
> define_int CONFIG_XILINX_V20_0_DEV_MIR_ENABLE 0
>
> define_string CONFIG_XILINX_V20_0_INSTANCE mb_opb
>
> define_string CONFIG_XILINX_V20_0_HW_VER 1.10.c
>
> # Definitions for MDM_0
>
> define_string CONFIG_XILINX_MDM_0_INSTANCE debug_module
>
> define_hex CONFIG_XILINX_MDM_0_BASEADDR 0x41400000
>
> define_hex CONFIG_XILINX_MDM_0_HIGHADDR 0x4140FFFF
>
> define_int CONFIG_XILINX_MDM_0_OPB_DWIDTH 32
>
> define_int CONFIG_XILINX_MDM_0_OPB_AWIDTH 32
>
> define_string CONFIG_XILINX_MDM_0_FAMILY virtex2p
>
> define_int CONFIG_XILINX_MDM_0_MB_DBG_PORTS 1
>
> define_int CONFIG_XILINX_MDM_0_USE_UART 0
>
> define_int CONFIG_XILINX_MDM_0_UART_WIDTH 8
>
> define_int CONFIG_XILINX_MDM_0_WRITE_FSL_PORTS 1
>
> define_string CONFIG_XILINX_MDM_0_INSTANCE debug_module
>
> define_string CONFIG_XILINX_MDM_0_HW_VER 2.00.a
>
> define_int CONFIG_XILINX_MDM_0_IRQ 0
>
> # Definitions for UARTLITE_0
>
> define_string CONFIG_XILINX_UARTLITE_0_INSTANCE RS232_DCE
>
> define_hex CONFIG_XILINX_UARTLITE_0_BASEADDR 0x40600000
>
> define_hex CONFIG_XILINX_UARTLITE_0_HIGHADDR 0x4060FFFF
>
> define_int CONFIG_XILINX_UARTLITE_0_OPB_DWIDTH 32
>
> define_int CONFIG_XILINX_UARTLITE_0_OPB_AWIDTH 32
>
> define_int CONFIG_XILINX_UARTLITE_0_DATA_BITS 8
>
> define_int CONFIG_XILINX_UARTLITE_0_CLK_FREQ 92000000
>
> define_int CONFIG_XILINX_UARTLITE_0_BAUDRATE 115200
>
> define_int CONFIG_XILINX_UARTLITE_0_USE_PARITY 0
>
> define_int CONFIG_XILINX_UARTLITE_0_ODD_PARITY 0
>
> define_string CONFIG_XILINX_UARTLITE_0_INSTANCE RS232_DCE
>
> define_string CONFIG_XILINX_UARTLITE_0_HW_VER 1.00.b
>
> define_int CONFIG_XILINX_UARTLITE_0_IRQ 3
>
> # Definitions for ETHERNETLITE_0
>
> define_string CONFIG_XILINX_ETHERNETLITE_0_INSTANCE Ethernet_MAC
>
> define_int CONFIG_XILINX_ETHERNETLITE_0_DUPLEX 1
>
> define_int CONFIG_XILINX_ETHERNETLITE_0_RX_PING_PONG 0
>
> define_int CONFIG_XILINX_ETHERNETLITE_0_TX_PING_PONG 0
>
> define_hex CONFIG_XILINX_ETHERNETLITE_0_BASEADDR 0x40E00000
>
> define_hex CONFIG_XILINX_ETHERNETLITE_0_HIGHADDR 0x40E0FFFF
>
> define_int CONFIG_XILINX_ETHERNETLITE_0_OPB_AWIDTH 32
>
> define_int CONFIG_XILINX_ETHERNETLITE_0_OPB_DWIDTH 32
>
> define_int CONFIG_XILINX_ETHERNETLITE_0_OPB_CLK_PERIOD_PS 10850
>
> define_string CONFIG_XILINX_ETHERNETLITE_0_FAMILY virtex2p
>
> define_string CONFIG_XILINX_ETHERNETLITE_0_INSTANCE Ethernet_MAC
>
> define_string CONFIG_XILINX_ETHERNETLITE_0_HW_VER 1.01.b
>
> define_int CONFIG_XILINX_ETHERNETLITE_0_IRQ 2
>
> # Definitions for MCH_OPB_DDR_0
>
> define_string CONFIG_XILINX_MCH_OPB_DDR_0_INSTANCE
> DDR_512MB_64Mx64_rank2_row13_col10_cl2_5
>
> define_string CONFIG_XILINX_MCH_OPB_DDR_0_FAMILY virtex2p
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_REG_DIMM 0
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_NUM_BANKS_MEM 1
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_NUM_CLK_PAIRS 4
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_ASYNC_SUPPORT 0
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_EXTRA_TSU 0
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_USE_OPEN_ROW_MNGT 0
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_INCLUDE_DDR_PIPE 1
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_NUM_CHANNELS 2
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_PRIORITY_MODE 0
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_INCLUDE_OPB_IPIF 1
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_INCLUDE_OPB_BURST_SUPPORT 0
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_INCLUDE_TIMEOUT_CNTR 0
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_TIMEOUT 16
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH_OPB_DWIDTH 32
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH_OPB_AWIDTH 32
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH_OPB_CLK_PERIOD_PS 10850
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TMRD 12000
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TWR 15000
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TWTR 1
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TRAS 42000
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TRC 60000
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TRFC 72000
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TRCD 18000
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TRRD 12000
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TREFI 7800000
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TRP 18000
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TXSR 80000
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_CAS_LAT 2
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_DWIDTH 64
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_AWIDTH 13
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_COL_AWIDTH 11
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_BANK_AWIDTH 2
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH0_PROTOCOL 0
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH0_ACCESSBUF_DEPTH 16
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH0_RDDATABUF_DEPTH 16
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH1_PROTOCOL 0
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH1_ACCESSBUF_DEPTH 16
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH1_RDDATABUF_DEPTH 16
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH2_PROTOCOL 0
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH2_ACCESSBUF_DEPTH 16
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH2_RDDATABUF_DEPTH 16
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH3_PROTOCOL 0
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH3_ACCESSBUF_DEPTH 16
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH3_RDDATABUF_DEPTH 16
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_XCL0_LINESIZE 4
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_XCL0_WRITEXFER 1
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_XCL1_LINESIZE 4
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_XCL1_WRITEXFER 1
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_XCL2_LINESIZE 4
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_XCL2_WRITEXFER 1
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_XCL3_LINESIZE 4
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_XCL3_WRITEXFER 1
>
> define_hex CONFIG_XILINX_MCH_OPB_DDR_0_MEM0_BASEADDR 0x22000000
>
> define_hex CONFIG_XILINX_MCH_OPB_DDR_0_MEM0_HIGHADDR 0x23FFFFFF
>
> define_hex CONFIG_XILINX_MCH_OPB_DDR_0_MEM1_BASEADDR 0xFFFFFFFF
>
> define_hex CONFIG_XILINX_MCH_OPB_DDR_0_MEM1_HIGHADDR 0x00000000
>
> define_hex CONFIG_XILINX_MCH_OPB_DDR_0_MEM2_BASEADDR 0xFFFFFFFF
>
> define_hex CONFIG_XILINX_MCH_OPB_DDR_0_MEM2_HIGHADDR 0x00000000
>
> define_hex CONFIG_XILINX_MCH_OPB_DDR_0_MEM3_BASEADDR 0xFFFFFFFF
>
> define_hex CONFIG_XILINX_MCH_OPB_DDR_0_MEM3_HIGHADDR 0x00000000
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_0_SIM_INIT_TIME_PS 100000000
>
> define_string CONFIG_XILINX_MCH_OPB_DDR_0_INSTANCE
> DDR_512MB_64Mx64_rank2_row13_col10_cl2_5
>
> define_string CONFIG_XILINX_MCH_OPB_DDR_0_HW_VER 1.00.b
>
> # Definitions for EMC_0
>
> define_string CONFIG_XILINX_EMC_0_INSTANCE SRAM_256Kx32_FLASH_2Mx32
>
> define_int CONFIG_XILINX_EMC_0_NUM_BANKS_MEM 1
>
> define_int CONFIG_XILINX_EMC_0_INCLUDE_BURST 0
>
> define_int CONFIG_XILINX_EMC_0_INCLUDE_NEGEDGE_IOREGS 0
>
> define_string CONFIG_XILINX_EMC_0_FAMILY virtex2p
>
> define_hex CONFIG_XILINX_EMC_0_MEM0_BASEADDR 0x21000000
>
> define_hex CONFIG_XILINX_EMC_0_MEM0_HIGHADDR 0x217FFFFF
>
> define_hex CONFIG_XILINX_EMC_0_MEM1_BASEADDR 0xFFFFFFFF
>
> define_hex CONFIG_XILINX_EMC_0_MEM1_HIGHADDR 0x00000000
>
> define_hex CONFIG_XILINX_EMC_0_MEM2_BASEADDR 0xFFFFFFFF
>
> define_hex CONFIG_XILINX_EMC_0_MEM2_HIGHADDR 0x00000000
>
> define_hex CONFIG_XILINX_EMC_0_MEM3_BASEADDR 0xFFFFFFFF
>
> define_hex CONFIG_XILINX_EMC_0_MEM3_HIGHADDR 0x00000000
>
> define_int CONFIG_XILINX_EMC_0_MEM0_WIDTH 32
>
> define_int CONFIG_XILINX_EMC_0_MEM1_WIDTH 32
>
> define_int CONFIG_XILINX_EMC_0_MEM2_WIDTH 32
>
> define_int CONFIG_XILINX_EMC_0_MEM3_WIDTH 32
>
> define_int CONFIG_XILINX_EMC_0_MAX_MEM_WIDTH 32
>
> define_int CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_0 0
>
> define_int CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_1 1
>
> define_int CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_2 1
>
> define_int CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_3 1
>
> define_int CONFIG_XILINX_EMC_0_SYNCH_MEM_0 0
>
> define_int CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_0 2
>
> define_int CONFIG_XILINX_EMC_0_TCEDV_PS_MEM_0 90000
>
> define_int CONFIG_XILINX_EMC_0_TAVDV_PS_MEM_0 90000
>
> define_int CONFIG_XILINX_EMC_0_THZCE_PS_MEM_0 10000
>
> define_int CONFIG_XILINX_EMC_0_THZOE_PS_MEM_0 7000
>
> define_int CONFIG_XILINX_EMC_0_TWC_PS_MEM_0 40000
>
> define_int CONFIG_XILINX_EMC_0_TWP_PS_MEM_0 40000
>
> define_int CONFIG_XILINX_EMC_0_TLZWE_PS_MEM_0 1000
>
> define_int CONFIG_XILINX_EMC_0_SYNCH_MEM_1 0
>
> define_int CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_1 2
>
> define_int CONFIG_XILINX_EMC_0_TCEDV_PS_MEM_1 15000
>
> define_int CONFIG_XILINX_EMC_0_TAVDV_PS_MEM_1 15000
>
> define_int CONFIG_XILINX_EMC_0_THZCE_PS_MEM_1 7000
>
> define_int CONFIG_XILINX_EMC_0_THZOE_PS_MEM_1 7000
>
> define_int CONFIG_XILINX_EMC_0_TWC_PS_MEM_1 15000
>
> define_int CONFIG_XILINX_EMC_0_TWP_PS_MEM_1 12000
>
> define_int CONFIG_XILINX_EMC_0_TLZWE_PS_MEM_1 0
>
> define_int CONFIG_XILINX_EMC_0_SYNCH_MEM_2 0
>
> define_int CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_2 2
>
> define_int CONFIG_XILINX_EMC_0_TCEDV_PS_MEM_2 15000
>
> define_int CONFIG_XILINX_EMC_0_TAVDV_PS_MEM_2 15000
>
> define_int CONFIG_XILINX_EMC_0_THZCE_PS_MEM_2 7000
>
> define_int CONFIG_XILINX_EMC_0_THZOE_PS_MEM_2 7000
>
> define_int CONFIG_XILINX_EMC_0_TWC_PS_MEM_2 15000
>
> define_int CONFIG_XILINX_EMC_0_TWP_PS_MEM_2 12000
>
> define_int CONFIG_XILINX_EMC_0_TLZWE_PS_MEM_2 0
>
> define_int CONFIG_XILINX_EMC_0_SYNCH_MEM_3 0
>
> define_int CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_3 2
>
> define_int CONFIG_XILINX_EMC_0_TCEDV_PS_MEM_3 15000
>
> define_int CONFIG_XILINX_EMC_0_TAVDV_PS_MEM_3 15000
>
> define_int CONFIG_XILINX_EMC_0_THZCE_PS_MEM_3 7000
>
> define_int CONFIG_XILINX_EMC_0_THZOE_PS_MEM_3 7000
>
> define_int CONFIG_XILINX_EMC_0_TWC_PS_MEM_3 15000
>
> define_int CONFIG_XILINX_EMC_0_TWP_PS_MEM_3 12000
>
> define_int CONFIG_XILINX_EMC_0_TLZWE_PS_MEM_3 0
>
> define_int CONFIG_XILINX_EMC_0_OPB_DWIDTH 32
>
> define_int CONFIG_XILINX_EMC_0_OPB_AWIDTH 32
>
> define_int CONFIG_XILINX_EMC_0_OPB_CLK_PERIOD_PS 10850
>
> define_string CONFIG_XILINX_EMC_0_INSTANCE SRAM_256Kx32_FLASH_2Mx32
>
> define_string CONFIG_XILINX_EMC_0_HW_VER 2.00.a
>
> # Definitions for TIMER_0
>
> define_string CONFIG_XILINX_TIMER_0_INSTANCE opb_timer_1
>
> define_string CONFIG_XILINX_TIMER_0_FAMILY virtex2p
>
> define_int CONFIG_XILINX_TIMER_0_COUNT_WIDTH 32
>
> define_int CONFIG_XILINX_TIMER_0_ONE_TIMER_ONLY 1
>
> define_int CONFIG_XILINX_TIMER_0_TRIG0_ASSERT 1
>
> define_int CONFIG_XILINX_TIMER_0_TRIG1_ASSERT 1
>
> define_int CONFIG_XILINX_TIMER_0_GEN0_ASSERT 1
>
> define_int CONFIG_XILINX_TIMER_0_GEN1_ASSERT 1
>
> define_int CONFIG_XILINX_TIMER_0_OPB_AWIDTH 32
>
> define_int CONFIG_XILINX_TIMER_0_OPB_DWIDTH 32
>
> define_hex CONFIG_XILINX_TIMER_0_BASEADDR 0x41C00000
>
> define_hex CONFIG_XILINX_TIMER_0_HIGHADDR 0x41C0FFFF
>
> define_string CONFIG_XILINX_TIMER_0_INSTANCE opb_timer_1
>
> define_string CONFIG_XILINX_TIMER_0_HW_VER 1.00.b
>
> define_int CONFIG_XILINX_TIMER_0_IRQ 1
>
> # Definitions for INTC_0
>
> define_string CONFIG_XILINX_INTC_0_INSTANCE opb_intc_0
>
> define_string CONFIG_XILINX_INTC_0_FAMILY virtex2p
>
> define_int CONFIG_XILINX_INTC_0_Y 0
>
> define_int CONFIG_XILINX_INTC_0_X 0
>
> define_string CONFIG_XILINX_INTC_0_U_SET intc
>
> define_int CONFIG_XILINX_INTC_0_OPB_AWIDTH 32
>
> define_int CONFIG_XILINX_INTC_0_OPB_DWIDTH 32
>
> define_hex CONFIG_XILINX_INTC_0_BASEADDR 0x41200000
>
> define_hex CONFIG_XILINX_INTC_0_HIGHADDR 0x4120FFFF
>
> define_int CONFIG_XILINX_INTC_0_NUM_INTR_INPUTS 4
>
> define_hex CONFIG_XILINX_INTC_0_KIND_OF_INTR 0x0000000D
>
> define_hex CONFIG_XILINX_INTC_0_KIND_OF_EDGE 0x0000000D
>
> define_hex CONFIG_XILINX_INTC_0_KIND_OF_LVL 0x00000002
>
> define_int CONFIG_XILINX_INTC_0_HAS_IPR 1
>
> define_int CONFIG_XILINX_INTC_0_HAS_SIE 1
>
> define_int CONFIG_XILINX_INTC_0_HAS_CIE 1
>
> define_int CONFIG_XILINX_INTC_0_HAS_IVR 1
>
> define_int CONFIG_XILINX_INTC_0_IRQ_IS_LEVEL 1
>
> define_int CONFIG_XILINX_INTC_0_IRQ_ACTIVE 1
>
> define_string CONFIG_XILINX_INTC_0_INSTANCE opb_intc_0
>
> define_string CONFIG_XILINX_INTC_0_HW_VER 1.00.c
>
> # Peripheral counts
>
> define_int CONFIG_XILINX_V20_NUM_INSTANCES 1
>
> define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_NUM_INSTANCES 2
>
> define_int CONFIG_XILINX_TIMER_NUM_INSTANCES 1
>
> define_int CONFIG_XILINX_EMC_NUM_INSTANCES 1
>
> define_int CONFIG_XILINX_MCH_OPB_DDR_NUM_INSTANCES 1
>
> define_int CONFIG_XILINX_ETHERNETLITE_NUM_INSTANCES 1
>
> define_int CONFIG_XILINX_INTC_NUM_INSTANCES 1
>
> define_int CONFIG_XILINX_UARTLITE_NUM_INSTANCES 1
>
> define_int CONFIG_XILINX_MDM_NUM_INSTANCES 1
>
>  
>
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