Re: [microblaze-uclinux] image.bin (2.4.32-uco) halted at address 0x24138000 ?autoconfig.h?

[gewent <gewent@xxxxxxxxx>]

Hi,
I noticed my linux-2.4.x/incude/linux/autoconfig.h has the old
addresses and not updated each time I do a make???

The file "auto-config.in"  in directory
linux-2.4.x/arch/microblaze/platform/uclinux-auto/ is up to date.

What tool do I use to force update of "autoconfig.h" from "auto-config.in"??

Thanks,
GW



On 10/21/07, gewent <gewent@xxxxxxxxx> wrote:
> Hi Benny,
> Yes readelf showed my code text start from 0x24000000 which is not
> correct for my MP. It should start from 0x44000000.
> But I double checked auto-config.in file it was correct.
>
> Do you know where I should go in the kernel to change the link address map?
>
> Thanks,
> GW
>
>
>
> On 10/21/07, Benny Chen <bennyc@xxxxxxxxxxxxxx> wrote:
> > Hi Gewent,
> > Check your image.elf file to see which address the image is linked.
> > This should tell you if your problem is due to building using a old
> > auto-config.in file.
> >
> > Benny Chen
> > gewent wrote:
> > > Hi,
> > > I need some expert help for my MB uClinux adventure. My uClinux image
> > > halted at memory address 0x24138000, as soon as it start to run. This
> > > address is not even on the MB processor memory map!?! I think there is
> > > something simple I am missing?
> > >
> > > Do I need to hack the boot address of ucLinux to 0x44000000 for MB
> > > ver6.0.b? I suppose this is done in auto configure script?
> > >
> > > Your expert out there, any hints or suggestion is highly appreciated.
> > >
> > > Thanks a lot,
> > > Gewent
> > >
> > >
> > > ====================================================
> > > Configuration and version information
> > > ====================================================
> > > Spartan-3E Starter Kit Rev.D (with XC3S500)
> > > Linux version 2.4.32-uco
> > > uClinux source is from xapp934 (VMWare+Centos 3.x+2.4x uclinux)
> > > Microblaze 6.00.b
> > > uClinux BSP v1.00d
> > > ISEwebpack 9.1, With all service pack   (Windows version)
> > > XPS9.1, With all service pack                (Windows version)
> > >
> > > Microblaze passes the simple memory test apps.
> > >
> > >
> > > ====================================================
> > > XMD LOG
> > > ====================================================
> > >
> > > Xilinx Microprocessor Debug (XMD) Engine
> > > Xilinx EDK 9.1.02 Build EDK_J_SP2.4
> > > Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
> > >
> > > XMD%
> > > Processor(s) in System ::
> > >
> > > Microblaze(1) : microblaze_0
> > > Address Map for Processor microblaze_0
> > >   (0000000000-0x00001fff) dlmb_cntlr    dlmb
> > >   (0000000000-0x00001fff) ilmb_cntlr    ilmb
> > >   (0x40000000-0x4000ffff) LEDs_8Bit     mb_opb
> > >   (0x40600000-0x4060ffff) RS232_DCE     mb_opb
> > >   (0x40c00000-0x40c0ffff) Ethernet_MAC  mb_opb
> > >   (0x41200000-0x4120ffff) opb_intc_0    mb_opb
> > >   (0x41400000-0x4140ffff) debug_module  mb_opb
> > >   (0x41c00000-0x41c0ffff) opb_timer_1   mb_opb
> > >   (0x44000000-0x47ffffff) DDR_SDRAM_32Mx16      mb_opb
> > >   (0x44000000-0x47ffffff) DDR_SDRAM_32Mx16      ixcl
> > >   (0x44000000-0x47ffffff) DDR_SDRAM_32Mx16      dxcl
> > >
> > > Info:AutoDetecting cable. Please wait.
> > > …… ……..
> > > JTAG chain configuration
> > > --------------------------------------------------
> > > Device   ID Code        IR Length    Part Name
> > >  1       01c22093           6        XC3S500E
> > >  2       05046093           8        XCF04S
> > >  3       06e5e093           8        XC2C64A_VQ44_1532
> > >
> > > MicroBlaze Processor Configuration :
> > > -------------------------------------
> > > Version............................6.00.b
> > > No of PC Breakpoints...............2
> > > No of Read Addr/Data Watchpoints...0
> > > No of Write Addr/Data Watchpoints..0
> > > Instruction Cache Support..........on
> > > Instruction Cache Base Address.....0x44000000
> > > Instruction Cache High Address.....0x47ffffff
> > > Data Cache Support.................on
> > > Data Cache Base Address............0x44000000
> > > Data Cache High Address............0x47ffffff
> > > Exceptions  Support................off
> > > FPU  Support.......................off
> > > Hard Divider Support...............on
> > > Hard Multiplier Support............on - (Mul32)
> > > Barrel Shifter Support.............on
> > > MSR clr/set Instruction Support....off
> > > Compare Instruction Support........on
> > >
> > > Connected to MDM UART Target
> > > Connected to "mb" target. id = 0
> > > Starting GDB server for "mb" target (id = 0) at TCP port no 1234
> > >
> > > XMD% dow -data image.bin 0x44000000
> > > XMD% con 0x44000000
> > > Info:Processor started. Type "stop" to stop processor
> > >
> > > RUNNING> XMD%
> > > XMD% stop
> > > XMD% Info:User Interrupt, Processor Stopped at 0x24138000
> > >
> > > XMD% bps 0x24138000
> > >
> > > ERROR(1061): Debug Memory Access Check Failed
> > >         Section, 0x24138000-0x24138003 Not Accessible from Processor
> > > Debug Interface
> > >
> > >
> > >
> > > ====================================================
> > > auto-config.in
> > > ====================================================
> > >
> > >
> > > ############################################################
> > > #
> > > # CAUTION: This file is automatically generated by libgen.
> > > # Version: Xilinx EDK 9.1.02 EDK_J_SP2.4
> > > # Description: uClinux Configuration File
> > > #
> > > ############################################################
> > >
> > >
> > >
> > > # MAIN_MEMORY Settings
> > > define_hex CONFIG_XILINX_ERAM_START 0x44000000
> > > define_hex CONFIG_XILINX_ERAM_SIZE 0x04000000
> > >
> > > # LMB_MEMORY Settings
> > > define_hex CONFIG_XILINX_LMB_START 0x00000000
> > > define_hex CONFIG_XILINX_LMB_SIZE 0x00002000
> > >
> > > # System Clock Frequency
> > > define_int CONFIG_XILINX_CPU_CLOCK_FREQ 66000000
> > >
> > > # Definitions for MICROBLAZE0
> > > define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
> > > define_int CONFIG_XILINX_MICROBLAZE0_SCO 0
> > > define_int CONFIG_XILINX_MICROBLAZE0_DATA_SIZE 32
> > > define_int CONFIG_XILINX_MICROBLAZE0_DYNAMIBUS_SIZING 1
> > > define_string CONFIG_XILINX_MICROBLAZE0_FAMILY spartan3e
> > > define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
> > > define_int CONFIG_XILINX_MICROBLAZE0_AREA_OPTIMIZED 1
> > > define_int CONFIG_XILINX_MICROBLAZE0_D_OPB 1
> > > define_int CONFIG_XILINX_MICROBLAZE0_D_LMB 1
> > > define_int CONFIG_XILINX_MICROBLAZE0_I_OPB 1
> > > define_int CONFIG_XILINX_MICROBLAZE0_I_LMB 1
> > > define_int CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR 0
> > > define_int CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR 1
> > > define_int CONFIG_XILINX_MICROBLAZE0_USE_BARREL 1
> > > define_int CONFIG_XILINX_MICROBLAZE0_USE_DIV 1
> > > define_int CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL 1
> > > define_int CONFIG_XILINX_MICROBLAZE0_USE_FPU 0
> > > define_int CONFIG_XILINX_MICROBLAZE0_UNALIGNED_EXCEPTIONS 0
> > > define_int CONFIG_XILINX_MICROBLAZE0_ILL_OPCODE_EXCEPTION 0
> > > define_int CONFIG_XILINX_MICROBLAZE0_IOPB_BUS_EXCEPTION 0
> > > define_int CONFIG_XILINX_MICROBLAZE0_DOPB_BUS_EXCEPTION 0
> > > define_int CONFIG_XILINX_MICROBLAZE0_DIV_ZERO_EXCEPTION 0
> > > define_int CONFIG_XILINX_MICROBLAZE0_FPU_EXCEPTION 0
> > > define_int CONFIG_XILINX_MICROBLAZE0_PVR 0
> > > define_hex CONFIG_XILINX_MICROBLAZE0_PVR_USER1 0x00000000
> > > define_hex CONFIG_XILINX_MICROBLAZE0_PVR_USER2 0x00000000
> > > define_int CONFIG_XILINX_MICROBLAZE0_DEBUG_ENABLED 1
> > > define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_PBRK 2
> > > define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_RD_ADDR_BRK 0
> > > define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_WR_ADDR_BRK 0
> > > define_int CONFIG_XILINX_MICROBLAZE0_INTERRUPT_IS_EDGE 0
> > > define_int CONFIG_XILINX_MICROBLAZE0_EDGE_IS_POSITIVE 1
> > > define_hex CONFIG_XILINX_MICROBLAZE0_RESET_MSR 0x00000000
> > > define_int CONFIG_XILINX_MICROBLAZE0_OPCODE_0X0_ILLEGAL 0
> > > define_int CONFIG_XILINX_MICROBLAZE0_FSL_LINKS 0
> > > define_int CONFIG_XILINX_MICROBLAZE0_FSL_DATA_SIZE 32
> > > define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_BASEADDR 0x44000000
> > > define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_HIGHADDR 0x47FFFFFF
> > > define_int CONFIG_XILINX_MICROBLAZE0_USE_ICACHE 1
> > > define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_ICACHE_WR 1
> > > define_int CONFIG_XILINX_MICROBLAZE0_ADDR_TAG_BITS 15
> > > define_int CONFIG_XILINX_MICROBLAZE0_CACHE_BYTE_SIZE 2048
> > > define_int CONFIG_XILINX_MICROBLAZE0_ICACHE_USE_FSL 1
> > > define_int CONFIG_XILINX_MICROBLAZE0_ICACHE_LINE_LEN 4
> > > define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_BASEADDR 0x44000000
> > > define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_HIGHADDR 0x47FFFFFF
> > > define_int CONFIG_XILINX_MICROBLAZE0_USE_DCACHE 1
> > > define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_DCACHE_WR 1
> > > define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_ADDR_TAG 13
> > > define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_BYTE_SIZE 8192
> > > define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_USE_FSL 1
> > > define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_LINE_LEN 4
> > > define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
> > > define_string CONFIG_XILINX_MICROBLAZE0_HW_VER 6.00.b
> > >
> > > # Definitions for LMB_BRAM_IF_CNTLR_0
> > > define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE dlmb_cntlr
> > > define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_BASEADDR 0x00000000
> > > define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HIGHADDR 0x00001FFF
> > > define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_MASK 0x40000000
> > > define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_AWIDTH 32
> > > define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_DWIDTH 32
> > > define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE dlmb_cntlr
> > > define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HW_VER 2.00.a
> > >
> > > # Definitions for LMB_BRAM_IF_CNTLR_1
> > > define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE ilmb_cntlr
> > > define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_BASEADDR 0x00000000
> > > define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HIGHADDR 0x00001FFF
> > > define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_MASK 0x40000000
> > > define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_AWIDTH 32
> > > define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_DWIDTH 32
> > > define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE ilmb_cntlr
> > > define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HW_VER 2.00.a
> > >
> > > # Definitions for V20_0
> > > define_string CONFIG_XILINX_V20_0_INSTANCE mb_opb
> > > define_hex CONFIG_XILINX_V20_0_BASEADDR 0xFFFFFFFF
> > > define_hex CONFIG_XILINX_V20_0_HIGHADDR 0x00000000
> > > define_int CONFIG_XILINX_V20_0_OPB_AWIDTH 32
> > > define_int CONFIG_XILINX_V20_0_OPB_DWIDTH 32
> > > define_int CONFIG_XILINX_V20_0_NUM_MASTERS 2
> > > define_int CONFIG_XILINX_V20_0_NUM_SLAVES 7
> > > define_int CONFIG_XILINX_V20_0_USE_LUT_OR 1
> > > define_int CONFIG_XILINX_V20_0_EXT_RESET_HIGH 1
> > > define_int CONFIG_XILINX_V20_0_DYNAM_PRIORITY 0
> > > define_int CONFIG_XILINX_V20_0_PARK 0
> > > define_int CONFIG_XILINX_V20_0_PROINTRFCE 0
> > > define_int CONFIG_XILINX_V20_0_REG_GRANTS 1
> > > define_int CONFIG_XILINX_V20_0_DEV_BLK_ID 0
> > > define_int CONFIG_XILINX_V20_0_DEV_MIR_ENABLE 0
> > > define_string CONFIG_XILINX_V20_0_INSTANCE mb_opb
> > > define_string CONFIG_XILINX_V20_0_HW_VER 1.10.c
> > >
> > > # Definitions for MDM_0
> > > define_string CONFIG_XILINX_MDM_0_INSTANCE debug_module
> > > define_hex CONFIG_XILINX_MDM_0_BASEADDR 0x41400000
> > > define_hex CONFIG_XILINX_MDM_0_HIGHADDR 0x4140FFFF
> > > define_int CONFIG_XILINX_MDM_0_OPB_DWIDTH 32
> > > define_int CONFIG_XILINX_MDM_0_OPB_AWIDTH 32
> > > define_string CONFIG_XILINX_MDM_0_FAMILY spartan3e
> > > define_int CONFIG_XILINX_MDM_0_MB_DBG_PORTS 1
> > > define_int CONFIG_XILINX_MDM_0_USE_UART 1
> > > define_int CONFIG_XILINX_MDM_0_UART_WIDTH 8
> > > define_int CONFIG_XILINX_MDM_0_WRITE_FSL_PORTS 0
> > > define_string CONFIG_XILINX_MDM_0_INSTANCE debug_module
> > > define_string CONFIG_XILINX_MDM_0_HW_VER 2.00.a
> > >
> > > # Definitions for UARTLITE_0
> > > define_string CONFIG_XILINX_UARTLITE_0_INSTANCE RS232_DCE
> > > define_hex CONFIG_XILINX_UARTLITE_0_BASEADDR 0x40600000
> > > define_hex CONFIG_XILINX_UARTLITE_0_HIGHADDR 0x4060FFFF
> > > define_int CONFIG_XILINX_UARTLITE_0_OPB_DWIDTH 32
> > > define_int CONFIG_XILINX_UARTLITE_0_OPB_AWIDTH 32
> > > define_int CONFIG_XILINX_UARTLITE_0_DATA_BITS 8
> > > define_int CONFIG_XILINX_UARTLITE_0_CLK_FREQ 66666667
> > > define_int CONFIG_XILINX_UARTLITE_0_BAUDRATE 9600
> > > define_int CONFIG_XILINX_UARTLITE_0_USE_PARITY 0
> > > define_int CONFIG_XILINX_UARTLITE_0_ODD_PARITY 0
> > > define_string CONFIG_XILINX_UARTLITE_0_INSTANCE RS232_DCE
> > > define_string CONFIG_XILINX_UARTLITE_0_HW_VER 1.00.b
> > > define_int CONFIG_XILINX_UARTLITE_0_IRQ 2
> > >
> > > # Definitions for GPIO_0
> > > define_string CONFIG_XILINX_GPIO_0_INSTANCE LEDs_8Bit
> > > define_hex CONFIG_XILINX_GPIO_0_BASEADDR 0x40000000
> > > define_hex CONFIG_XILINX_GPIO_0_HIGHADDR 0x4000FFFF
> > > define_int CONFIG_XILINX_GPIO_0_USER_ID_CODE 3
> > > define_int CONFIG_XILINX_GPIO_0_OPB_AWIDTH 32
> > > define_int CONFIG_XILINX_GPIO_0_OPB_DWIDTH 32
> > > define_string CONFIG_XILINX_GPIO_0_FAMILY spartan3e
> > > define_int CONFIG_XILINX_GPIO_0_GPIO_WIDTH 8
> > > define_int CONFIG_XILINX_GPIO_0_ALL_INPUTS 0
> > > define_int CONFIG_XILINX_GPIO_0_INTERRUPT_PRESENT 0
> > > define_int CONFIG_XILINX_GPIO_0_IS_BIDIR 0
> > > define_hex CONFIG_XILINX_GPIO_0_DOUT_DEFAULT 0x00000000
> > > define_hex CONFIG_XILINX_GPIO_0_TRI_DEFAULT 0xFFFFFFFF
> > > define_int CONFIG_XILINX_GPIO_0_IS_DUAL 0
> > > define_int CONFIG_XILINX_GPIO_0_ALL_INPUTS_2 0
> > > define_int CONFIG_XILINX_GPIO_0_IS_BIDIR_2 1
> > > define_hex CONFIG_XILINX_GPIO_0_DOUT_DEFAULT_2 0x00000000
> > > define_hex CONFIG_XILINX_GPIO_0_TRI_DEFAULT_2 0xFFFFFFFF
> > > define_string CONFIG_XILINX_GPIO_0_INSTANCE LEDs_8Bit
> > > define_string CONFIG_XILINX_GPIO_0_HW_VER 3.01.b
> > >
> > > # Definitions for MCH_OPB_DDR_0
> > > define_string CONFIG_XILINX_MCH_OPB_DDR_0_INSTANCE DDR_SDRAM_32Mx16
> > > define_string CONFIG_XILINX_MCH_OPB_DDR_0_FAMILY spartan3e
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_REG_DIMM 0
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_NUM_BANKS_MEM 1
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_NUM_CLK_PAIRS 1
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_ASYNSUPPORT 1
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_EXTRA_TSU 0
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_USE_OPEN_ROW_MNGT 0
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_INCLUDE_DDR_PIPE 1
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_NUM_CHANNELS 2
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_PRIORITY_MODE 0
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_INCLUDE_OPB_IPIF 1
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_INCLUDE_OPB_BURST_SUPPORT 0
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_INCLUDE_TIMEOUT_CNTR 0
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_TIMEOUT 16
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH_OPB_DWIDTH 32
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH_OPB_AWIDTH 32
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH_OPB_CLK_PERIOD_PS 14999
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TMRD 15000
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TWR 15000
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TWTR 1
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TRAS 42000
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TRC 65000
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TRFC 75000
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TRCD 20000
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TRRD 15000
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TREFI 7800000
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TRP 20000
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_TXSR 80000
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_CAS_LAT 2
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_DWIDTH 16
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_AWIDTH 13
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_COL_AWIDTH 10
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_DDR_BANK_AWIDTH 2
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH0_PROTOCOL 0
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH0_ACCESSBUF_DEPTH 16
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH0_RDDATABUF_DEPTH 0
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH1_PROTOCOL 0
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH1_ACCESSBUF_DEPTH 16
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH1_RDDATABUF_DEPTH 0
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH2_PROTOCOL 0
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH2_ACCESSBUF_DEPTH 16
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH2_RDDATABUF_DEPTH 16
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH3_PROTOCOL 0
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH3_ACCESSBUF_DEPTH 16
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_MCH3_RDDATABUF_DEPTH 16
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_XCL0_LINESIZE 4
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_XCL0_WRITEXFER 0
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_XCL1_LINESIZE 4
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_XCL1_WRITEXFER 1
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_XCL2_LINESIZE 4
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_XCL2_WRITEXFER 1
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_XCL3_LINESIZE 4
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_XCL3_WRITEXFER 1
> > > define_hex CONFIG_XILINX_MCH_OPB_DDR_0_MEM0_BASEADDR 0x44000000
> > > define_hex CONFIG_XILINX_MCH_OPB_DDR_0_MEM0_HIGHADDR 0x47FFFFFF
> > > define_hex CONFIG_XILINX_MCH_OPB_DDR_0_MEM1_BASEADDR 0xFFFFFFFF
> > > define_hex CONFIG_XILINX_MCH_OPB_DDR_0_MEM1_HIGHADDR 0x00000000
> > > define_hex CONFIG_XILINX_MCH_OPB_DDR_0_MEM2_BASEADDR 0xFFFFFFFF
> > > define_hex CONFIG_XILINX_MCH_OPB_DDR_0_MEM2_HIGHADDR 0x00000000
> > > define_hex CONFIG_XILINX_MCH_OPB_DDR_0_MEM3_BASEADDR 0xFFFFFFFF
> > > define_hex CONFIG_XILINX_MCH_OPB_DDR_0_MEM3_HIGHADDR 0x00000000
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_0_SIM_INIT_TIME_PS 100000000
> > > define_string CONFIG_XILINX_MCH_OPB_DDR_0_INSTANCE DDR_SDRAM_32Mx16
> > > define_string CONFIG_XILINX_MCH_OPB_DDR_0_HW_VER 1.00.c
> > >
> > > # Definitions for ETHERNET_0
> > > define_string CONFIG_XILINX_ETHERNET_0_INSTANCE Ethernet_MAC
> > > define_int CONFIG_XILINX_ETHERNET_0_DEV_BLK_ID 1
> > > define_int CONFIG_XILINX_ETHERNET_0_DEV_MIR_ENABLE 1
> > > define_hex CONFIG_XILINX_ETHERNET_0_BASEADDR 0x40C00000
> > > define_hex CONFIG_XILINX_ETHERNET_0_HIGHADDR 0x40C0FFFF
> > > define_int CONFIG_XILINX_ETHERNET_0_RESET_PRESENT 1
> > > define_int CONFIG_XILINX_ETHERNET_0_INCLUDE_DEV_PENCODER 1
> > > define_int CONFIG_XILINX_ETHERNET_0_DMA_PRESENT 1
> > > define_int CONFIG_XILINX_ETHERNET_0_DMA_INTR_COALESCE 1
> > > define_int CONFIG_XILINX_ETHERNET_0_OPB_AWIDTH 32
> > > define_int CONFIG_XILINX_ETHERNET_0_OPB_DWIDTH 32
> > > define_int CONFIG_XILINX_ETHERNET_0_OPB_CLK_PERIOD_PS 14999
> > > define_string CONFIG_XILINX_ETHERNET_0_FAMILY spartan3e
> > > define_int CONFIG_XILINX_ETHERNET_0_IPIF_RDFIFO_DEPTH 32768
> > > define_int CONFIG_XILINX_ETHERNET_0_IPIF_WRFIFO_DEPTH 32768
> > > define_hex CONFIG_XILINX_ETHERNET_0_MIIM_CLKDVD 0x0000001F
> > > define_int CONFIG_XILINX_ETHERNET_0_SOURCE_ADDR_INSERT_EXIST 1
> > > define_int CONFIG_XILINX_ETHERNET_0_PAD_INSERT_EXIST 1
> > > define_int CONFIG_XILINX_ETHERNET_0_FCS_INSERT_EXIST 1
> > > define_int CONFIG_XILINX_ETHERNET_0_MAFIFO_DEPTH 64
> > > define_int CONFIG_XILINX_ETHERNET_0_MAFIFO_BRAM_1_SRL_0 0
> > > define_int CONFIG_XILINX_ETHERNET_0_HALF_DUPLEX_EXIST 1
> > > define_int CONFIG_XILINX_ETHERNET_0_ERR_COUNT_EXIST 1
> > > define_int CONFIG_XILINX_ETHERNET_0_CAM_EXIST 0
> > > define_int CONFIG_XILINX_ETHERNET_0_CAM_BRAM_0_SRL_1 1
> > > define_int CONFIG_XILINX_ETHERNET_0_JUMBO_EXIST 0
> > > define_int CONFIG_XILINX_ETHERNET_0_MII_EXIST 1
> > > define_int CONFIG_XILINX_ETHERNET_0_TX_DRE_TYPE 0
> > > define_int CONFIG_XILINX_ETHERNET_0_RX_DRE_TYPE 0
> > > define_int CONFIG_XILINX_ETHERNET_0_TX_INCLUDE_CSUM 0
> > > define_int CONFIG_XILINX_ETHERNET_0_RX_INCLUDE_CSUM 0
> > > define_string CONFIG_XILINX_ETHERNET_0_INSTANCE Ethernet_MAC
> > > define_string CONFIG_XILINX_ETHERNET_0_HW_VER 1.04.a
> > > define_int CONFIG_XILINX_ETHERNET_0_IRQ 1
> > >
> > > # Definitions for TIMER_0
> > > define_string CONFIG_XILINX_TIMER_0_INSTANCE opb_timer_1
> > > define_string CONFIG_XILINX_TIMER_0_FAMILY spartan3e
> > > define_int CONFIG_XILINX_TIMER_0_COUNT_WIDTH 32
> > > define_int CONFIG_XILINX_TIMER_0_ONE_TIMER_ONLY 1
> > > define_int CONFIG_XILINX_TIMER_0_TRIG0_ASSERT 1
> > > define_int CONFIG_XILINX_TIMER_0_TRIG1_ASSERT 1
> > > define_int CONFIG_XILINX_TIMER_0_GEN0_ASSERT 1
> > > define_int CONFIG_XILINX_TIMER_0_GEN1_ASSERT 1
> > > define_int CONFIG_XILINX_TIMER_0_OPB_AWIDTH 32
> > > define_int CONFIG_XILINX_TIMER_0_OPB_DWIDTH 32
> > > define_hex CONFIG_XILINX_TIMER_0_BASEADDR 0x41C00000
> > > define_hex CONFIG_XILINX_TIMER_0_HIGHADDR 0x41C0FFFF
> > > define_string CONFIG_XILINX_TIMER_0_INSTANCE opb_timer_1
> > > define_string CONFIG_XILINX_TIMER_0_HW_VER 1.00.b
> > > define_int CONFIG_XILINX_TIMER_0_IRQ 0
> > >
> > > # Definitions for INTC_0
> > > define_string CONFIG_XILINX_INTC_0_INSTANCE opb_intc_0
> > > define_string CONFIG_XILINX_INTC_0_FAMILY spartan3e
> > > define_int CONFIG_XILINX_INTC_0_Y 0
> > > define_int CONFIG_XILINX_INTC_0_X 0
> > > define_string CONFIG_XILINX_INTC_0_U_SET intc
> > > define_int CONFIG_XILINX_INTC_0_OPB_AWIDTH 32
> > > define_int CONFIG_XILINX_INTC_0_OPB_DWIDTH 32
> > > define_hex CONFIG_XILINX_INTC_0_BASEADDR 0x41200000
> > > define_hex CONFIG_XILINX_INTC_0_HIGHADDR 0x4120FFFF
> > > define_int CONFIG_XILINX_INTC_0_NUM_INTR_INPUTS 3
> > > define_hex CONFIG_XILINX_INTC_0_KIND_OF_INTR 0x00000004
> > > define_hex CONFIG_XILINX_INTC_0_KIND_OF_EDGE 0x00000004
> > > define_hex CONFIG_XILINX_INTC_0_KIND_OF_LVL 0x00000003
> > > define_int CONFIG_XILINX_INTC_0_HAS_IPR 1
> > > define_int CONFIG_XILINX_INTC_0_HAS_SIE 1
> > > define_int CONFIG_XILINX_INTC_0_HAS_CIE 1
> > > define_int CONFIG_XILINX_INTC_0_HAS_IVR 1
> > > define_int CONFIG_XILINX_INTC_0_IRQ_IS_LEVEL 1
> > > define_int CONFIG_XILINX_INTC_0_IRQ_ACTIVE 1
> > > define_string CONFIG_XILINX_INTC_0_INSTANCE opb_intc_0
> > > define_string CONFIG_XILINX_INTC_0_HW_VER 1.00.c
> > >
> > > # Peripheral counts
> > > define_int CONFIG_XILINX_V20_NUM_INSTANCES 1
> > > define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_NUM_INSTANCES 2
> > > define_int CONFIG_XILINX_TIMER_NUM_INSTANCES 1
> > > define_int CONFIG_XILINX_MCH_OPB_DDR_NUM_INSTANCES 1
> > > define_int CONFIG_XILINX_INTC_NUM_INSTANCES 1
> > > define_int CONFIG_XILINX_UARTLITE_NUM_INSTANCES 1
> > > define_int CONFIG_XILINX_MDM_NUM_INSTANCES 1
> > > define_int CONFIG_XILINX_ETHERNET_NUM_INSTANCES 1
> > > define_int CONFIG_XILINX_GPIO_NUM_INSTANCES 1
> > >
> > >
> > > ====================================================
> > > end
> > > ====================================================
> > >
> > > ___________________________
> > > microblaze-uclinux mailing list
> > > microblaze-uclinux@xxxxxxxxxxxxxx
> > > Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
> > > Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
> > >
> > >
> > ___________________________
> > microblaze-uclinux mailing list
> > microblaze-uclinux@xxxxxxxxxxxxxx
> > Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
> > Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
> >
> >
>

___________________________
microblaze-uclinux mailing list
microblaze-uclinux@xxxxxxxxxxxxxx
Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/