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RE: [microblaze-uclinux] EDK91 SP2 BSB Digilent S3E500 Rev D
For Rev D board, I have the DCM location fixed to have better timing. (based on BSB generated design)
NET fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<*> NODELAY;
NET fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_pin<*> NODELAY;
INST "dcm_0/dcm_0/Using_Virtex.DCM_INST" LOC = DCM_X0Y1;
INST "dcm_0/dcm_0/Using_BUGF_for_CLK2X.CLK2X_BUFG_INST" LOC = BUFGMUX_X1Y11;
INST "dcm_0/dcm_0/Using_BUGF_for_CLK0.CLK0_BUFG_INST" LOC = BUFGMUX_X2Y10;
INST "dcm_1/dcm_1/Using_Virtex.DCM_INST" LOC = DCM_X1Y0;
INST "dcm_1/dcm_1/Using_BUGF_for_CLK90.CLK90_BUFG_INST" LOC = BUFGMUX_X2Y0;
INST "dcm_1/dcm_1/Using_BUGF_for_CLK0.CLK0_BUFG_INST" LOC = BUFGMUX_X2Y1;
INST "dcm_2/dcm_2/Using_Virtex.DCM_INST" LOC = DCM_X1Y1;
INST "dcm_2/dcm_2/Using_BUGF_for_CLK90.CLK90_BUFG_INST" LOC = BUFGMUX_X1Y10;
INST "dcm_2/dcm_2/Using_BUGF_for_CLK0.CLK0_BUFG_INST" LOC = BUFGMUX_X2Y11;
INST "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" LOC = BUFGMUX_X1Y0;
INST "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" LOC = BUFGMUX_X1Y1;
Ps. S3E500 starter board FPGA is small, it's recommend to use opb_ethernet_lite
-Kevin
-----Original Message-----
From: owner-microblaze-uclinux@xxxxxxxxxxxxxx [mailto:owner-microblaze-uclinux@xxxxxxxxxxxxxx] On Behalf Of LEGER
Sent: Monday, October 29, 2007 10:06 PM
To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: [microblaze-uclinux] EDK91 SP2 BSB Digilent S3E500 Rev D
Hi,
After a long time having headaches with the Digilent's Rev D boards, I got something fitting and working as I expected.
All the memory tests are OK over the 32MB of DDR SDRAM.
Softwares used: EDK 9.1.2 ISE 9.1.3
When using the standard Xilinx BSB, It seems we have these problems:
- even adding the following constraints in the UCF to the DDR signals :
access to the DDR sometimes fails.
NET fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<*> NODELAY; NET fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_pin<*> NODELAY;
- if you add some peripherals => timing closure can be invalid, or at least access to the DDR sometimes fails.
- the S3E500 has only 4 DCMs -> the tools have problems to connect the 3 DCM.
- the BSB instanciates too much BUFG -> I got a warning on synthesis and with floorplanner I can see clock paths jumping side to side of the chip....
- the reset circuit is not based on the proc_sys_reset => only OPB_rst for all peripherals => the placement is hawfull.
I used the reference design XAPP909 to implement a proc_sys_reset architecture.
I suppressed all the BUFG I think useless.
Under Floorplanner the placement is much better distributed across the chip.
There is no warning remaining on the DCM/BUFG placement.
I am not sure it is the right place to post this UCF and MHS files.
Sorry if it is not, I hope it helps.
Best regards,
Frédéric LEGER
Transfert de Technologie
ESISAR - INPG
50 rue Barthélémy de Laffemas
BP54 - 26902 Valence Cedex 9
Tel: +33(0)475759475
Fax: +33(0)475435642
web: http://www.esisar.inpg.fr
############################################################################
## This system.ucf file is generated by Base System Builder based on the ## settings in the selected Xilinx Board Definition file. Please add other ## user constraints to this file based on customer design specifications.
############################################################################
NET fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<*> NODELAY; NET fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_pin<*> NODELAY;
Net sys_clk_pin LOC=c9;
Net sys_clk_pin IOSTANDARD = LVCMOS33;
Net sys_rst_pin LOC=K17;
Net sys_rst_pin IOSTANDARD = LVCMOS33;
Net sys_rst_pin PULLDOWN;
## System level constraints
Net sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 20000 ps; Net sys_rst_pin TIG; Net fpga_0_DDR_CLK_FB LOC=B9; Net fpga_0_DDR_CLK_FB IOSTANDARD = LVCMOS33;
## IO Devices constraints
#### Module RS232_DCE constraints
Net fpga_0_RS232_DCE_RX_pin LOC=R7;
Net fpga_0_RS232_DCE_RX_pin IOSTANDARD = LVCMOS33; Net fpga_0_RS232_DCE_TX_pin LOC=M14; Net fpga_0_RS232_DCE_TX_pin IOSTANDARD = LVCMOS33;
#### Module LEDs_8Bit constraints
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<0> LOC=F9; Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<0> IOSTANDARD = LVCMOS33; Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<1> LOC=E9; Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<1> IOSTANDARD = LVCMOS33; Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<2> LOC=D11; Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<2> IOSTANDARD = LVCMOS33; Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<3> LOC=C11; Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<3> IOSTANDARD = LVCMOS33; Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<4> LOC=F11; Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<4> IOSTANDARD = LVCMOS33; Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<5> LOC=E11; Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<5> IOSTANDARD = LVCMOS33; Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<6> LOC=E12; Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<6> IOSTANDARD = LVCMOS33; Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<7> LOC=F12; Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<7> IOSTANDARD = LVCMOS33;
#### Module DDR_SDRAM_32Mx16 constraints
Net fpga_0_DDR_SDRAM_32Mx16_DDR_Clk_pin LOC=J5; Net fpga_0_DDR_SDRAM_32Mx16_DDR_Clk_pin IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_Clkn_pin LOC=J4; Net fpga_0_DDR_SDRAM_32Mx16_DDR_Clkn_pin IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<0> LOC=P2; Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<0> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<1> LOC=N5; Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<1> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<2> LOC=T2; Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<2> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<3> LOC=N4; Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<3> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<4> LOC=H2; Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<4> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<5> LOC=H1; Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<5> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<6> LOC=H3; Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<6> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<7> LOC=H4; Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<7> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<8> LOC=F4; Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<8> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<9> LOC=P1; Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<9> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<10> LOC=R2; Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<10> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<11> LOC=R3; Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<11> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<12> LOC=T1; Net fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin<12> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr_pin<0> LOC=K6; Net fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr_pin<0> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr_pin<1> LOC=K5; Net fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr_pin<1> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx!
16_DDR_C
ASn_pin LOC=C2; Net fpga_0_DDR_SDRAM_32Mx16_DDR_CASn_pin IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_CKE_pin LOC=K3; Net fpga_0_DDR_SDRAM_32Mx16_DDR_CKE_pin IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_CSn_pin LOC=K4; Net fpga_0_DDR_SDRAM_32Mx16_DDR_CSn_pin IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_RASn_pin LOC=C1; Net fpga_0_DDR_SDRAM_32Mx16_DDR_RASn_pin IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_WEn_pin LOC=D1; Net fpga_0_DDR_SDRAM_32Mx16_DDR_WEn_pin IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DM_pin<0> LOC=J1; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DM_pin<0> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DM_pin<1> LOC=J2; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DM_pin<1> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_pin<0> LOC=G3; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_pin<0> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_pin<1> LOC=L6; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_pin<1> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_pin<1> PULLUP; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<0> LOC=H5; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<0> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<0> PULLUP; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<1> LOC=H6; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<1> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<1> PULLUP; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<2> LOC=G5; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<2> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<2> PULLUP; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<3> LOC=G6; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<3> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<3> PULLUP; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<4> LOC=F2; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<4> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<4> PULLUP; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<5> LOC=F1; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<5> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<5> PULLUP; Net fpga_0_DDR_SDRAM_32!
Mx16_DDR
_DQ_pin<6> LOC=E1; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<6> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<6> PULLUP; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<7> LOC=E2; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<7> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<7> PULLUP; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<8> LOC=M6; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<8> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<8> PULLUP; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<9> LOC=M5; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<9> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<9> PULLUP; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<10> LOC=M4; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<10> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<10> PULLUP; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<11> LOC=M3; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<11> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<11> PULLUP; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<12> LOC=L4; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<12> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<12> PULLUP; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<13> LOC=L3; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<13> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<13> PULLUP; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<14> LOC=L1; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<14> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<14> PULLUP; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<15> LOC=L2; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<15> IOSTANDARD = SSTL2_I; Net fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin<15> PULLUP;
#### Module Ethernet_MAC constraints
Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin LOC=T7; Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin IOSTANDARD = LVCMOS33; Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin LOC=V3; Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin IOSTANDARD = LVCMOS33; Net fpga_0_Ethernet_MAC_PHY_crs_pin LOC=U13; Net fpga_0_Ethernet_MAC_PHY_crs_pin IOSTANDARD = LVCMOS33; Net fpga_0_Ethernet_MAC_PHY_dv_pin LOC=V2; Net fpga_0_Ethernet_MAC_PHY_dv_pin IOSTANDARD = LVCMOS33; Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> LOC=V8; Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> IOSTANDARD = LVCMOS33; Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> LOC=T11; Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> IOSTANDARD = LVCMOS33; Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> LOC=U11; Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> IOSTANDARD = LVCMOS33; Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> LOC=V14; Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> IOSTANDARD = LVCMOS33; Net fpga_0_Ethernet_MAC_PHY_col_pin LOC=U6; Net fpga_0_Ethernet_MAC_PHY_col_pin IOSTANDARD = LVCMOS33; Net fpga_0_Ethernet_MAC_PHY_rx_er_pin LOC=U14; Net fpga_0_Ethernet_MAC_PHY_rx_er_pin IOSTANDARD = LVCMOS33; Net fpga_0_Ethernet_MAC_PHY_tx_en_pin LOC=P15; Net fpga_0_Ethernet_MAC_PHY_tx_en_pin IOSTANDARD = LVCMOS33; Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> LOC=R11; Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> IOSTANDARD = LVCMOS33; Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> LOC=T15; Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> IOSTANDARD = LVCMOS33; Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> LOC=R5; Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> IOSTANDARD = LVCMOS33; Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> LOC=T5; Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> IOSTANDARD = LVCMOS33;
Net fpga_0_DDR_CLK_FB TNM_NET = fpga_0_DDR_CLK_FB; TIMESPEC TS_fpga_0_DDR_CLK_FB = PERIOD fpga_0_DDR_CLK_FB 10000 ps;
#
############################################################################
##
# Created by Base System Builder Wizard for Xilinx EDK 9.1.02 Build
EDK_J_SP2.4
# Mon Oct 29 09:47:43 2007
# Target Board: Xilinx Spartan-3E Starter Board Rev D
# Family: spartan3e
# Device: XC3S500e
# Package: FG320
# Speed Grade: -4
# Processor: Microblaze
# System clock frequency: 50.000000 MHz
# Debug interface: On-Chip HW Debug Module
# On Chip Memory : 8 KB
# Total Off Chip Memory : 64 MB
# - DDR_SDRAM_32Mx16 = 64 MB
#
############################################################################
##
PARAMETER VERSION = 2.1.0
PORT fpga_0_RS232_DCE_RX_pin = fpga_0_RS232_DCE_RX, DIR = I PORT fpga_0_RS232_DCE_TX_pin = fpga_0_RS232_DCE_TX, DIR = O PORT fpga_0_LEDs_8Bit_GPIO_d_out_pin = fpga_0_LEDs_8Bit_GPIO_d_out, DIR = O, VEC = [0:7] PORT fpga_0_DDR_SDRAM_32Mx16_DDR_Clk_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_Clk, DIR = O PORT fpga_0_DDR_SDRAM_32Mx16_DDR_Clkn_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_Clkn, DIR = O PORT fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_Addr, DIR = O, VEC = [0:12] PORT fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr, DIR = O, VEC = [0:1] PORT fpga_0_DDR_SDRAM_32Mx16_DDR_CASn_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_CASn, DIR = O PORT fpga_0_DDR_SDRAM_32Mx16_DDR_CKE_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_CKE, DIR = O PORT fpga_0_DDR_SDRAM_32Mx16_DDR_CSn_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_CSn, DIR = O PORT fpga_0_DDR_SDRAM_32Mx16_DDR_RASn_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_RASn, DIR = O PORT fpga_0_DDR_SDRAM_32Mx16_DDR_WEn_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_WEn, DIR = O PORT fpga_0_DDR_SDRAM_32Mx16_DDR_DM_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_DM, DIR = O, VEC = [0:1] PORT fpga_0_DDR_SDRAM_32Mx16_DDR_DQS_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_DQS, DIR = IO, VEC = [0:1] PORT fpga_0_DDR_SDRAM_32Mx16_DDR_DQ_pin = fpga_0_DDR_SDRAM_32Mx16_DDR_DQ, DIR = IO, VEC = [0:15] PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk, DIR = I PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk, DIR = I PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs, DIR = I PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv, DIR = I PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data, DIR = I, VEC = [3:0] PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col, DIR = I PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er, DIR = I PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en, DIR = O PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_t!
x_data,
DIR = O, VEC = [3:0] PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RST
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 6.00.b
PARAMETER C_USE_FPU = 0
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_NUMBER_OF_PC_BRK = 2
PARAMETER C_USE_ICACHE = 1
PARAMETER C_CACHE_BYTE_SIZE = 8192
PARAMETER C_USE_DCACHE = 1
PARAMETER C_DCACHE_BYTE_SIZE = 8192
PARAMETER C_ICACHE_BASEADDR = 0x44000000 PARAMETER C_ICACHE_HIGHADDR = 0x47ffffff PARAMETER C_DCACHE_BASEADDR = 0x44000000 PARAMETER C_DCACHE_HIGHADDR = 0x47ffffff PARAMETER C_AREA_OPTIMIZED = 1 PARAMETER C_USE_BARREL = 1 PARAMETER C_USE_DIV = 1 BUS_INTERFACE DLMB = dlmb BUS_INTERFACE ILMB = ilmb BUS_INTERFACE DOPB = mb_opb BUS_INTERFACE IOPB = mb_opb BUS_INTERFACE IXCL = ixcl BUS_INTERFACE DXCL = dxcl PORT DBG_CAPTURE = DBG_CAPTURE_s PORT DBG_CLK = DBG_CLK_s PORT DBG_REG_EN = DBG_REG_EN_s PORT DBG_TDI = DBG_TDI_s PORT DBG_TDO = DBG_TDO_s PORT DBG_UPDATE = DBG_UPDATE_s PORT Interrupt = Interrupt PORT RESET = microblaze_rst END
BEGIN opb_v20
PARAMETER INSTANCE = mb_opb
PARAMETER HW_VER = 1.10.c
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = bus_rst_opb
PORT OPB_Clk = sys_clk_s
END
BEGIN opb_mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 2.00.a
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER C_UART_WIDTH = 8
PARAMETER C_BASEADDR = 0x41400000
PARAMETER C_HIGHADDR = 0x4140ffff
BUS_INTERFACE SOPB = mb_opb
PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
PORT DBG_CLK_0 = DBG_CLK_s
PORT DBG_REG_EN_0 = DBG_REG_EN_s
PORT DBG_TDI_0 = DBG_TDI_s
PORT DBG_TDO_0 = DBG_TDO_s
PORT DBG_UPDATE_0 = DBG_UPDATE_s
PORT OPB_Rst = periph_rst_0
PORT Debug_SYS_Rst = Debug_SYS_Rst
PORT Debug_Rst = Debug_Rst
END
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = bus_rst_ilmb
PORT LMB_Clk = sys_clk_s
END
BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = bus_rst_dlmb
PORT LMB_Clk = sys_clk_s
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
PORT LMB_Rst = periph_rst_1
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
PORT LMB_Rst = periph_rst_2
END
BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
PORT BRAM_Rst_A = periph_rst_3
PORT BRAM_Rst_B = periph_rst_4
END
BEGIN opb_uartlite
PARAMETER INSTANCE = RS232_DCE
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 115200
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_CLK_FREQ = 50000000
PARAMETER C_BASEADDR = 0x40600000
PARAMETER C_HIGHADDR = 0x4060ffff
BUS_INTERFACE SOPB = mb_opb
PORT Interrupt = RS232_DCE_Interrupt
PORT RX = fpga_0_RS232_DCE_RX
PORT TX = fpga_0_RS232_DCE_TX
PORT OPB_Rst = periph_rst_5
END
BEGIN opb_gpio
PARAMETER INSTANCE = LEDs_8Bit
PARAMETER HW_VER = 3.01.b
PARAMETER C_GPIO_WIDTH = 8
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_BASEADDR = 0x40000000
PARAMETER C_HIGHADDR = 0x4000ffff
BUS_INTERFACE SOPB = mb_opb
PORT GPIO_d_out = fpga_0_LEDs_8Bit_GPIO_d_out PORT OPB_Rst = periph_rst_6 END
BEGIN mch_opb_ddr
PARAMETER INSTANCE = DDR_SDRAM_32Mx16
PARAMETER HW_VER = 1.00.c
PARAMETER C_INCLUDE_OPB_BURST_SUPPORT = 0 PARAMETER C_XCL0_WRITEXFER = 0 PARAMETER C_MCH0_ACCESSBUF_DEPTH = 16 PARAMETER C_MCH1_ACCESSBUF_DEPTH = 16 PARAMETER C_MCH_OPB_CLK_PERIOD_PS = 20000 PARAMETER C_REG_DIMM = 0 PARAMETER C_DDR_TMRD = 15000 PARAMETER C_DDR_TWR = 15000 PARAMETER C_DDR_TWTR = 1 PARAMETER C_DDR_TRAS = 42000 PARAMETER C_DDR_TRC = 65000 PARAMETER C_DDR_TRFC = 75000 PARAMETER C_DDR_TRCD = 20000 PARAMETER C_DDR_TRRD = 15000 PARAMETER C_DDR_TRP = 20000 PARAMETER C_DDR_TREFI = 7800000 PARAMETER C_DDR_DWIDTH = 16 PARAMETER C_DDR_AWIDTH = 13 PARAMETER C_DDR_COL_AWIDTH = 10 PARAMETER C_MCH0_RDDATABUF_DEPTH = 0 PARAMETER C_XCL0_LINESIZE = 4 PARAMETER C_MCH1_RDDATABUF_DEPTH = 0 PARAMETER C_XCL1_LINESIZE = 4 PARAMETER C_XCL1_WRITEXFER = 1 PARAMETER C_DDR_BANK_AWIDTH = 2 PARAMETER C_DDR_ASYNC_SUPPORT = 1 PARAMETER C_NUM_CLK_PAIRS = 1 PARAMETER C_MEM0_BASEADDR = 0x44000000 PARAMETER C_MEM0_HIGHADDR = 0x47ffffff BUS_INTERFACE SOPB = mb_opb BUS_INTERFACE MCH0 = ixcl BUS_INTERFACE MCH1 = dxcl PORT DDR_Clk = fpga_0_DDR_SDRAM_32Mx16_DDR_Clk PORT DDR_Clkn = fpga_0_DDR_SDRAM_32Mx16_DDR_Clkn PORT DDR_Addr = fpga_0_DDR_SDRAM_32Mx16_DDR_Addr PORT DDR_BankAddr = fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr
PORT DDR_CASn = fpga_0_DDR_SDRAM_32Mx16_DDR_CASn PORT DDR_CKE = fpga_0_DDR_SDRAM_32Mx16_DDR_CKE PORT DDR_CSn = fpga_0_DDR_SDRAM_32Mx16_DDR_CSn PORT DDR_RASn = fpga_0_DDR_SDRAM_32Mx16_DDR_RASn PORT DDR_WEn = fpga_0_DDR_SDRAM_32Mx16_DDR_WEn PORT DDR_DM = fpga_0_DDR_SDRAM_32Mx16_DDR_DM PORT DDR_DQS = fpga_0_DDR_SDRAM_32Mx16_DDR_DQS PORT DDR_DQ = fpga_0_DDR_SDRAM_32Mx16_DDR_DQ PORT Device_Clk90_in = ddr_dev_clk_90_s PORT Device_Clk90_in_n = ddr_dev_clk_90_s_n PORT Device_Clk = ddr_dev_clk_s PORT Device_Clk_n = ddr_dev_clk_s_n PORT DDR_Clk90_in = ddr_clk_90_s PORT DDR_Clk90_in_n = ddr_clk_90_n_s PORT MCH_OPB_Rst = periph_rst_7 END
BEGIN opb_ethernetlite
PARAMETER INSTANCE = Ethernet_MAC
PARAMETER HW_VER = 1.01.b
PARAMETER C_OPB_CLK_PERIOD_PS = 20000
PARAMETER C_BASEADDR = 0x40e00000
PARAMETER C_HIGHADDR = 0x40e0ffff
BUS_INTERFACE SOPB = mb_opb
PORT IP2INTC_Irpt = Ethernet_MAC_IP2INTC_Irpt PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data PORT OPB_Rst = periph_rst_9 END
BEGIN opb_timer
PARAMETER INSTANCE = opb_timer_1
PARAMETER HW_VER = 1.00.b
PARAMETER C_COUNT_WIDTH = 32
PARAMETER C_ONE_TIMER_ONLY = 1
PARAMETER C_BASEADDR = 0x41c00000
PARAMETER C_HIGHADDR = 0x41c0ffff
BUS_INTERFACE SOPB = mb_opb
PORT Interrupt = opb_timer_1_Interrupt
PORT OPB_Rst = periph_rst_10
END
BEGIN opb_intc
PARAMETER INSTANCE = opb_intc_0
PARAMETER HW_VER = 1.00.c
PARAMETER C_BASEADDR = 0x41200000
PARAMETER C_HIGHADDR = 0x4120ffff
BUS_INTERFACE SOPB = mb_opb
PORT Irq = Interrupt
PORT Intr = RS232_DCE_Interrupt & Ethernet_MAC_IP2INTC_Irpt & opb_timer_1_Interrupt PORT OPB_Rst = periph_rst_8 END
BEGIN util_vector_logic
PARAMETER INSTANCE = devclk_inv
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE = 1
PARAMETER C_OPERATION = not
PORT Op1 = ddr_dev_clk_s
PORT Res = ddr_dev_clk_s_n
END
BEGIN util_vector_logic
PARAMETER INSTANCE = devclk90_inv
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE = 1
PARAMETER C_OPERATION = not
PORT Op1 = ddr_dev_clk_90_s
PORT Res = ddr_dev_clk_90_s_n
END
BEGIN util_vector_logic
PARAMETER INSTANCE = ddr_clk90_inv
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE = 1
PARAMETER C_OPERATION = not
PORT Op1 = ddr_clk_90_s
PORT Res = ddr_clk_90_n_s
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_0
PARAMETER HW_VER = 1.00.c
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLK2X_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 20.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_EXT_RESET_HIGH = 1
PORT CLKIN = dcm_clk_s
PORT CLK0 = sys_clk_s
PORT CLKFB = sys_clk_s
PORT CLK2X = dcm_0CLK2X
PORT RST = net_gnd
PORT LOCKED = dcm_0_lock
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_1
PARAMETER HW_VER = 1.00.c
PARAMETER C_CLK0_BUF = FALSE
PARAMETER C_CLK90_BUF = FALSE
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_EXT_RESET_HIGH = 0
PORT CLKIN = dcm_0CLK2X
PORT CLK0 = ddr_dev_clk_s
PORT CLK90 = ddr_dev_clk_90_s
PORT CLKFB = ddr_dev_clk_s
PORT RST = dcm_0_lock
PORT LOCKED = dcm_1_lock
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_2
PARAMETER HW_VER = 1.00.c
PARAMETER C_CLK0_BUF = FALSE
PARAMETER C_CLK90_BUF = FALSE
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_EXT_RESET_HIGH = 0
PORT CLKIN = ddr_feedback_s
PORT CLK90 = ddr_clk_90_s
PORT CLK0 = dcm_2_FB
PORT CLKFB = dcm_2_FB
PORT RST = dcm_1_lock
PORT LOCKED = dcm_2_lock
END
BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_NUM_BUS_RST = 3
PARAMETER C_NUM_PERP_RST = 11
PORT Slowest_sync_clk = sys_clk_s
PORT Bus_Struct_Reset = bus_rst_opb& bus_rst_ilmb & bus_rst_dlmb PORT Ext_Reset_In = sys_rst_s PORT Aux_Reset_In = net_gnd PORT Core_Reset_Req = Debug_Rst PORT Chip_Reset_Req = net_gnd PORT System_Reset_Req = Debug_SYS_Rst PORT Rstc405resetcore = microblaze_rst PORT Dcm_locked = dcm_2_lock PORT Peripheral_Reset = periph_rst_0&periph_rst_1&periph_rst_2&periph_rst_3&periph_rst_4&periph_rst_
5&periph_rst_6&periph_rst_7&periph_rst_8&periph_rst_9&periph_rst_10
END
/*
*
* Xilinx, Inc.
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE.
*/
/*
* Xilinx EDK 9.1.02 EDK_J_SP2.4
*
* This file is a sample test application
*
* This application is intended to test and/or illustrate some
* functionality of your system. The contents of this file may
* vary depending on the IP in your system and may use existing
* IP driver functions. These drivers will be generated in your
* XPS project when you run the "Generate Libraries" menu item
* in XPS.
*
* Your XPS project directory is at:
* C:\Designs\S3E912\
*/
// Located in: microblaze_0/include/xparameters.h
#include "xparameters.h"
#include "mb_interface.h"
#include "stdio.h"
#include "xutil.h"
//====================================================
int main (void) {
/*
* Enable and initialize cache
*/
#if XPAR_MICROBLAZE_0_USE_ICACHE
microblaze_init_icache_range(0, XPAR_MICROBLAZE_0_CACHE_BYTE_SIZE);
microblaze_enable_icache();
#endif
#if XPAR_MICROBLAZE_0_USE_DCACHE
microblaze_init_dcache_range(0, XPAR_MICROBLAZE_0_DCACHE_BYTE_SIZE);
microblaze_enable_dcache();
#endif
print("-- Entering main() --\r\n");
/*
* MemoryTest routine will not be run for the memory at
* 0x00000000 (dlmb_cntlr)
* because it is being used to hold a part of this application program
*/
/* Testing SDRAM Memory (DDR_SDRAM_32Mx16)*/
{
XStatus status;
print("Starting MemoryTest for DDR_SDRAM_32Mx16:\r\n");
print(" Running 32-bit test...");
status =
XUtil_MemoryTest32((Xuint32*)XPAR_DDR_SDRAM_32MX16_MEM0_BASEADDR,
2*4096*1024, 0xAAAA5555, XUT_ALLMEMTESTS);
if (status == XST_SUCCESS) {
print("PASSED!\r\n");
}
else {
print("FAILED!\r\n");
}
print(" Running 16-bit test...");
status =
XUtil_MemoryTest16((Xuint16*)XPAR_DDR_SDRAM_32MX16_MEM0_BASEADDR,
2*4096*2048, 0xAA55, XUT_ALLMEMTESTS);
if (status == XST_SUCCESS) {
print("PASSED!\r\n");
}
else {
print("FAILED!\r\n");
}
print(" Running 8-bit test...");
status =
XUtil_MemoryTest8((Xuint8*)XPAR_DDR_SDRAM_32MX16_MEM0_BASEADDR, 2*4096*4096,
0xA5, XUT_ALLMEMTESTS);
if (status == XST_SUCCESS) {
print("PASSED!\r\n");
}
else {
print("FAILED!\r\n");
}
}
/*
* Disable cache and reinitialize it so that other
* applications can be run with no problems
*/
#if XPAR_MICROBLAZE_0_USE_DCACHE
microblaze_disable_dcache();
microblaze_init_dcache_range(0, XPAR_MICROBLAZE_0_DCACHE_BYTE_SIZE);
#endif
#if XPAR_MICROBLAZE_0_USE_ICACHE
microblaze_disable_icache();
microblaze_init_icache_range(0, XPAR_MICROBLAZE_0_CACHE_BYTE_SIZE);
#endif
print("-- Exiting main() --\r\n");
return 0;
}
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Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
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___________________________
microblaze-uclinux mailing list
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Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/