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RE: [microblaze-uclinux] RE: [microblaze-uclinux] [uClinux-dev] problems downloading image.bin for kernel 2.6
Here is my KConfig.auto.
Right now I have no flash, another processor downloads the image.bin
file to DDR at 0x3000_0000 and then FS-Boot just branches to this
address. 0x3000_0000 is the beginning of my memory. Is this ok?
Which .config file do you want? There are several here...
Ken
############################################################
#
# CAUTION: This file is automatically generated by libgen.
# EDK Version: Xilinx EDK 9.1.02 EDK_J_SP2.4
# Description: PetaLinux Configuration File - Kernel Version 2.6.x
#
############################################################
# MAIN_MEMORY Settings
comment "MAIN_MEMORY Settings"
depends on ALLOW_EDIT_AUTO
config XILINX_ERAM_START
hex "Start address of XILINX_ERAM" if ALLOW_EDIT_AUTO
default 0x30000000
config XILINX_ERAM_SIZE
hex "Size of XILINX_ERAM" if ALLOW_EDIT_AUTO
default 0x08000000
# System Clock Frequency
comment "System Clock Frequency"
depends on ALLOW_EDIT_AUTO
config XILINX_CPU_CLOCK_FREQ
int "System Clock Frequency (Hz)" if ALLOW_EDIT_AUTO
default 60000000
# Definitions for MICROBLAZE0
comment "Definitions for MICROBLAZE0"
depends on ALLOW_EDIT_AUTO
config XILINX_MICROBLAZE0_INSTANCE
string "Core Instance Name" if ALLOW_EDIT_AUTO
default "microblaze_0"
config XILINX_MICROBLAZE0_SCO
int "SCO" if ALLOW_EDIT_AUTO
default 0
config XILINX_MICROBLAZE0_DATA_SIZE
int "DATA_SIZE" if ALLOW_EDIT_AUTO
default 32
config XILINX_MICROBLAZE0_DYNAMIC_BUS_SIZING
int "DYNAMIC_BUS_SIZING" if ALLOW_EDIT_AUTO
default 1
config XILINX_MICROBLAZE0_FAMILY
string "Targetted FPGA family" if ALLOW_EDIT_AUTO
default "virtex5"
config XILINX_MICROBLAZE0_INSTANCE
string "INSTANCE" if ALLOW_EDIT_AUTO
default "microblaze_0"
config XILINX_MICROBLAZE0_AREA_OPTIMIZED
int "AREA_OPTIMIZED range (0:1)" if ALLOW_EDIT_AUTO
default 0
config XILINX_MICROBLAZE0_D_OPB
int "D_OPB" if ALLOW_EDIT_AUTO
default 1
config XILINX_MICROBLAZE0_D_LMB
int "D_LMB" if ALLOW_EDIT_AUTO
default 1
config XILINX_MICROBLAZE0_I_OPB
int "I_OPB" if ALLOW_EDIT_AUTO
default 1
config XILINX_MICROBLAZE0_I_LMB
int "I_LMB" if ALLOW_EDIT_AUTO
default 1
config XILINX_MICROBLAZE0_USE_MSR_INSTR
int "USE_MSR_INSTR range (0:1)" if ALLOW_EDIT_AUTO
default 1
config XILINX_MICROBLAZE0_USE_PCMP_INSTR
int "USE_PCMP_INSTR range (0:1)" if ALLOW_EDIT_AUTO
default 1
config XILINX_MICROBLAZE0_USE_BARREL
int "USE_BARREL range (0:1)" if ALLOW_EDIT_AUTO
default 0
config XILINX_MICROBLAZE0_USE_DIV
int "USE_DIV range (0:1)" if ALLOW_EDIT_AUTO
default 0
config XILINX_MICROBLAZE0_USE_HW_MUL
int "USE_HW_MUL values 0= NONE, 1= MUL32, 2= MUL64" if
ALLOW_EDIT_AUTO
default 1
config XILINX_MICROBLAZE0_USE_FPU
int "USE_FPU range (0:1)" if ALLOW_EDIT_AUTO
default 0
config XILINX_MICROBLAZE0_UNALIGNED_EXCEPTIONS
int "UNALIGNED_EXCEPTIONS range (0:1)" if ALLOW_EDIT_AUTO
default 0
config XILINX_MICROBLAZE0_ILL_OPCODE_EXCEPTION
int "ILL_OPCODE_EXCEPTION range (0:1)" if ALLOW_EDIT_AUTO
default 0
config XILINX_MICROBLAZE0_IOPB_BUS_EXCEPTION
int "IOPB_BUS_EXCEPTION" if ALLOW_EDIT_AUTO
default 0
config XILINX_MICROBLAZE0_DOPB_BUS_EXCEPTION
int "DOPB_BUS_EXCEPTION" if ALLOW_EDIT_AUTO
default 0
config XILINX_MICROBLAZE0_DIV_ZERO_EXCEPTION
int "DIV_ZERO_EXCEPTION range (0:C_USE_DIV)" if ALLOW_EDIT_AUTO
default 0
config XILINX_MICROBLAZE0_FPU_EXCEPTION
int "FPU_EXCEPTION range (0:1)" if ALLOW_EDIT_AUTO
default 0
config XILINX_MICROBLAZE0_PVR
int "PVR values 0= NONE, 1= BASIC, 2= FULL" if ALLOW_EDIT_AUTO
default 0
config XILINX_MICROBLAZE0_PVR_USER1
hex "PVR_USER1" if ALLOW_EDIT_AUTO
default 0x00000000
config XILINX_MICROBLAZE0_PVR_USER2
hex "PVR_USER2" if ALLOW_EDIT_AUTO
default 0x00000000
config XILINX_MICROBLAZE0_DEBUG_ENABLED
int "DEBUG_ENABLED range (0:1)" if ALLOW_EDIT_AUTO
default 1
config XILINX_MICROBLAZE0_NUMBER_OF_PC_BRK
int "NUMBER_OF_PC_BRK range (0:8)" if ALLOW_EDIT_AUTO
default 4
config XILINX_MICROBLAZE0_NUMBER_OF_RD_ADDR_BRK
int "NUMBER_OF_RD_ADDR_BRK range (0:4)" if ALLOW_EDIT_AUTO
default 2
config XILINX_MICROBLAZE0_NUMBER_OF_WR_ADDR_BRK
int "NUMBER_OF_WR_ADDR_BRK range (0:4)" if ALLOW_EDIT_AUTO
default 2
config XILINX_MICROBLAZE0_INTERRUPT_IS_EDGE
int "INTERRUPT_IS_EDGE range (0:1)" if ALLOW_EDIT_AUTO
default 0
config XILINX_MICROBLAZE0_EDGE_IS_POSITIVE
int "EDGE_IS_POSITIVE range (0:1)" if ALLOW_EDIT_AUTO
default 1
config XILINX_MICROBLAZE0_RESET_MSR
hex "RESET_MSR values 0x0000= NONE, 0x0020= ICE, 0x0080= DCE,
0x00a0= ICE_DCE" if ALLOW_EDIT_AUTO
default 0x00000000
config XILINX_MICROBLAZE0_OPCODE_0X0_ILLEGAL
int "OPCODE_0x0_ILLEGAL range (0:1)" if ALLOW_EDIT_AUTO
default 0
config XILINX_MICROBLAZE0_FSL_LINKS
int "FSL_LINKS range (0:8)" if ALLOW_EDIT_AUTO
default 0
config XILINX_MICROBLAZE0_FSL_DATA_SIZE
int "FSL_DATA_SIZE" if ALLOW_EDIT_AUTO
default 32
config XILINX_MICROBLAZE0_ICACHE_BASEADDR
hex "ICACHE_BASEADDR" if ALLOW_EDIT_AUTO
default 0x00000000
config XILINX_MICROBLAZE0_ICACHE_HIGHADDR
hex "ICACHE_HIGHADDR" if ALLOW_EDIT_AUTO
default 0x3FFFFFFF
config XILINX_MICROBLAZE0_USE_ICACHE
int "USE_ICACHE range (0:1)" if ALLOW_EDIT_AUTO
default 0
config XILINX_MICROBLAZE0_ALLOW_ICACHE_WR
int "ALLOW_ICACHE_WR range (0:1)" if ALLOW_EDIT_AUTO
default 1
config XILINX_MICROBLAZE0_ADDR_TAG_BITS
int "ADDR_TAG_BITS range (0:25)" if ALLOW_EDIT_AUTO
default 0
config XILINX_MICROBLAZE0_CACHE_BYTE_SIZE
int "CACHE_BYTE_SIZE values 64= 64B, 128= 128B, 256= 256B, 512=
512B, 1024= 1kB, 2048= 2kB,4096= 4kB,8192= 8kB,16384= 16kB,32768=
32kB,65536= 64kB" if ALLOW_EDIT_AUTO
default 8192
config XILINX_MICROBLAZE0_ICACHE_USE_FSL
int "ICACHE_USE_FSL" if ALLOW_EDIT_AUTO
default 1
config XILINX_MICROBLAZE0_ICACHE_LINE_LEN
int "ICACHE_LINE_LEN range (4, 8)" if ALLOW_EDIT_AUTO
default 4
config XILINX_MICROBLAZE0_DCACHE_BASEADDR
hex "DCACHE_BASEADDR" if ALLOW_EDIT_AUTO
default 0x00000000
config XILINX_MICROBLAZE0_DCACHE_HIGHADDR
hex "DCACHE_HIGHADDR" if ALLOW_EDIT_AUTO
default 0x3FFFFFFF
config XILINX_MICROBLAZE0_USE_DCACHE
int "USE_DCACHE range (0:1)" if ALLOW_EDIT_AUTO
default 0
config XILINX_MICROBLAZE0_ALLOW_DCACHE_WR
int "ALLOW_DCACHE_WR range (0:1)" if ALLOW_EDIT_AUTO
default 1
config XILINX_MICROBLAZE0_DCACHE_ADDR_TAG
int "DCACHE_ADDR_TAG range (0:25)" if ALLOW_EDIT_AUTO
default 0
config XILINX_MICROBLAZE0_DCACHE_BYTE_SIZE
int "DCACHE_BYTE_SIZE values 64= 64B, 128= 128B, 256= 256B, 512=
512B, 1024= 1kB, 2048= 2kB,4096= 4kB,8192= 8kB,16384= 16kB,32768=
32kB,65536= 64kB" if ALLOW_EDIT_AUTO
default 8192
config XILINX_MICROBLAZE0_DCACHE_USE_FSL
int "DCACHE_USE_FSL" if ALLOW_EDIT_AUTO
default 1
config XILINX_MICROBLAZE0_DCACHE_LINE_LEN
int "DCACHE_LINE_LEN range (4, 8)" if ALLOW_EDIT_AUTO
default 4
config XILINX_MICROBLAZE0_INSTANCE
string "Core Instance Name" if ALLOW_EDIT_AUTO
default "microblaze_0"
config XILINX_MICROBLAZE0_HW_VER
string "Core version number" if ALLOW_EDIT_AUTO
default "6.00.b"
# Definitions for LMB_BRAM_IF_CNTLR_0
comment "Definitions for LMB_BRAM_IF_CNTLR_0"
depends on ALLOW_EDIT_AUTO
config XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE
string "Core Instance Name" if ALLOW_EDIT_AUTO
default "dlmb_cntlr"
config XILINX_LMB_BRAM_IF_CNTLR_0_BASEADDR
hex "Base address" if ALLOW_EDIT_AUTO
default 0x00000000
config XILINX_LMB_BRAM_IF_CNTLR_0_HIGHADDR
hex "High address" if ALLOW_EDIT_AUTO
default 0x00007FFF
config XILINX_LMB_BRAM_IF_CNTLR_0_MASK
hex "MASK" if ALLOW_EDIT_AUTO
default 0x20000000
config XILINX_LMB_BRAM_IF_CNTLR_0_LMB_AWIDTH
int "LMB_AWIDTH" if ALLOW_EDIT_AUTO
default 32
config XILINX_LMB_BRAM_IF_CNTLR_0_LMB_DWIDTH
int "LMB_DWIDTH" if ALLOW_EDIT_AUTO
default 32
config XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE
string "Core Instance Name" if ALLOW_EDIT_AUTO
default "dlmb_cntlr"
config XILINX_LMB_BRAM_IF_CNTLR_0_HW_VER
string "Core version number" if ALLOW_EDIT_AUTO
default "2.00.a"
# Definitions for LMB_BRAM_IF_CNTLR_1
comment "Definitions for LMB_BRAM_IF_CNTLR_1"
depends on ALLOW_EDIT_AUTO
config XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE
string "Core Instance Name" if ALLOW_EDIT_AUTO
default "ilmb_cntlr"
config XILINX_LMB_BRAM_IF_CNTLR_1_BASEADDR
hex "Base address" if ALLOW_EDIT_AUTO
default 0x00000000
config XILINX_LMB_BRAM_IF_CNTLR_1_HIGHADDR
hex "High address" if ALLOW_EDIT_AUTO
default 0x00007FFF
config XILINX_LMB_BRAM_IF_CNTLR_1_MASK
hex "MASK" if ALLOW_EDIT_AUTO
default 0x20000000
config XILINX_LMB_BRAM_IF_CNTLR_1_LMB_AWIDTH
int "LMB_AWIDTH" if ALLOW_EDIT_AUTO
default 32
config XILINX_LMB_BRAM_IF_CNTLR_1_LMB_DWIDTH
int "LMB_DWIDTH" if ALLOW_EDIT_AUTO
default 32
config XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE
string "Core Instance Name" if ALLOW_EDIT_AUTO
default "ilmb_cntlr"
config XILINX_LMB_BRAM_IF_CNTLR_1_HW_VER
string "Core version number" if ALLOW_EDIT_AUTO
default "2.00.a"
# Definitions for V20_0
comment "Definitions for V20_0"
depends on ALLOW_EDIT_AUTO
config XILINX_V20_0_INSTANCE
string "Core Instance Name" if ALLOW_EDIT_AUTO
default "mb_opb"
config XILINX_V20_0_BASEADDR
hex "Base address" if ALLOW_EDIT_AUTO
default 0xFFFFFFFF
config XILINX_V20_0_HIGHADDR
hex "High address" if ALLOW_EDIT_AUTO
default 0x00000000
config XILINX_V20_0_OPB_AWIDTH
int "OPB_AWIDTH" if ALLOW_EDIT_AUTO
default 32
config XILINX_V20_0_OPB_DWIDTH
int "OPB_DWIDTH" if ALLOW_EDIT_AUTO
default 32
config XILINX_V20_0_NUM_MASTERS
int "NUM_MASTERS" if ALLOW_EDIT_AUTO
default 4
config XILINX_V20_0_NUM_SLAVES
int "NUM_SLAVES" if ALLOW_EDIT_AUTO
default 9
config XILINX_V20_0_USE_LUT_OR
int "USE_LUT_OR range (0,1)" if ALLOW_EDIT_AUTO
default 1
config XILINX_V20_0_EXT_RESET_HIGH
int "EXT_RESET_HIGH range (0,1)" if ALLOW_EDIT_AUTO
default 0
config XILINX_V20_0_DYNAM_PRIORITY
int "DYNAM_PRIORITY range (0,1)" if ALLOW_EDIT_AUTO
default 0
config XILINX_V20_0_PARK
int "PARK range (0,1)" if ALLOW_EDIT_AUTO
default 0
config XILINX_V20_0_PROC_INTRFCE
int "PROC_INTRFCE range (0,1)" if ALLOW_EDIT_AUTO
default 0
config XILINX_V20_0_REG_GRANTS
int "REG_GRANTS range (0,1)" if ALLOW_EDIT_AUTO
default 1
config XILINX_V20_0_DEV_BLK_ID
int "DEV_BLK_ID range (0:255)" if ALLOW_EDIT_AUTO
default 0
config XILINX_V20_0_DEV_MIR_ENABLE
int "DEV_MIR_ENABLE range (0,1)" if ALLOW_EDIT_AUTO
default 0
config XILINX_V20_0_INSTANCE
string "Core Instance Name" if ALLOW_EDIT_AUTO
default "mb_opb"
config XILINX_V20_0_HW_VER
string "Core version number" if ALLOW_EDIT_AUTO
default "1.10.c"
# Definitions for IP_OPB2PIO_0
comment "Definitions for IP_OPB2PIO_0"
depends on ALLOW_EDIT_AUTO
config XILINX_IP_OPB2PIO_0_INSTANCE
string "Core Instance Name" if ALLOW_EDIT_AUTO
default "ip_opb2pio_0"
config XILINX_IP_OPB2PIO_0_BASEADDR
hex "Base address" if ALLOW_EDIT_AUTO
default 0x22500000
config XILINX_IP_OPB2PIO_0_HIGHADDR
hex "High address" if ALLOW_EDIT_AUTO
default 0x2250FFFF
config XILINX_IP_OPB2PIO_0_OPB_AWIDTH
int "OPB_AWIDTH" if ALLOW_EDIT_AUTO
default 32
config XILINX_IP_OPB2PIO_0_OPB_DWIDTH
int "OPB_DWIDTH range (8, 16, 32)" if ALLOW_EDIT_AUTO
default 32
config XILINX_IP_OPB2PIO_0_FAMILY
string "Targetted FPGA family" if ALLOW_EDIT_AUTO
default "virtex5"
config XILINX_IP_OPB2PIO_0_AR0_BASEADDR
hex "AR0_BASEADDR" if ALLOW_EDIT_AUTO
default 0x25000000
config XILINX_IP_OPB2PIO_0_AR0_HIGHADDR
hex "AR0_HIGHADDR" if ALLOW_EDIT_AUTO
default 0x2503FFFF
config XILINX_IP_OPB2PIO_0_MCH_OPB_CLK_PERIOD_PS
int "MCH_OPB_CLK_PERIOD_PS" if ALLOW_EDIT_AUTO
default 16666
config XILINX_IP_OPB2PIO_0_PIO_RD_PERIOD_PS
int "PIO_RD_PERIOD_PS" if ALLOW_EDIT_AUTO
default 35000
config XILINX_IP_OPB2PIO_0_PIO_WR_PERIOD_PS
int "PIO_WR_PERIOD_PS" if ALLOW_EDIT_AUTO
default 23000
config XILINX_IP_OPB2PIO_0_PIO_B2B_PERIOD_PS
int "PIO_B2B_PERIOD_PS" if ALLOW_EDIT_AUTO
default 36000
config XILINX_IP_OPB2PIO_0_INSTANCE
string "Core Instance Name" if ALLOW_EDIT_AUTO
default "ip_opb2pio_0"
config XILINX_IP_OPB2PIO_0_HW_VER
string "Core version number" if ALLOW_EDIT_AUTO
default "1.00.a"
config XILINX_IP_OPB2PIO_0_IRQ
int "IRQ number of IP_OPB2PIO_0" if ALLOW_EDIT_AUTO
default 2
# Definitions for GPIF2OPB_MASTER_NOFIFO_0
comment "Definitions for GPIF2OPB_MASTER_NOFIFO_0"
depends on ALLOW_EDIT_AUTO
config XILINX_GPIF2OPB_MASTER_NOFIFO_0_INSTANCE
string "Core Instance Name" if ALLOW_EDIT_AUTO
default "gpif2opb_master_nofifo_0"
config XILINX_GPIF2OPB_MASTER_NOFIFO_0_BASEADDR
hex "Base address" if ALLOW_EDIT_AUTO
default 0x22400000
config XILINX_GPIF2OPB_MASTER_NOFIFO_0_HIGHADDR
hex "High address" if ALLOW_EDIT_AUTO
default 0x2240000F
config XILINX_GPIF2OPB_MASTER_NOFIFO_0_OPB_AWIDTH
int "OPB_AWIDTH" if ALLOW_EDIT_AUTO
default 32
config XILINX_GPIF2OPB_MASTER_NOFIFO_0_OPB_DWIDTH
int "OPB_DWIDTH range (8, 16, 32)" if ALLOW_EDIT_AUTO
default 32
config XILINX_GPIF2OPB_MASTER_NOFIFO_0_USER_ID_CODE
int "USER_ID_CODE range (0:255)" if ALLOW_EDIT_AUTO
default 3
config XILINX_GPIF2OPB_MASTER_NOFIFO_0_FAMILY
string "Targetted FPGA family" if ALLOW_EDIT_AUTO
default "virtex5"
config XILINX_GPIF2OPB_MASTER_NOFIFO_0_INSTANCE
string "Core Instance Name" if ALLOW_EDIT_AUTO
default "gpif2opb_master_nofifo_0"
config XILINX_GPIF2OPB_MASTER_NOFIFO_0_HW_VER
string "Core version number" if ALLOW_EDIT_AUTO
default "2.01.a"
# Definitions for REGFILE_0
comment "Definitions for REGFILE_0"
depends on ALLOW_EDIT_AUTO
config XILINX_REGFILE_0_INSTANCE
string "Core Instance Name" if ALLOW_EDIT_AUTO
default "opb_regfile_0"
config XILINX_REGFILE_0_BASEADDR
hex "Base address" if ALLOW_EDIT_AUTO
default 0x23400000
config XILINX_REGFILE_0_HIGHADDR
hex "High address" if ALLOW_EDIT_AUTO
default 0x2340007F
config XILINX_REGFILE_0_OPB_AWIDTH
int "OPB_AWIDTH" if ALLOW_EDIT_AUTO
default 32
config XILINX_REGFILE_0_OPB_DWIDTH
int "OPB_DWIDTH" if ALLOW_EDIT_AUTO
default 32
config XILINX_REGFILE_0_FAMILY
string "Targetted FPGA family" if ALLOW_EDIT_AUTO
default "virtex5"
config XILINX_REGFILE_0_NUM_OF_REG
int "NUM_OF_REG range (1:32)" if ALLOW_EDIT_AUTO
default 32
config XILINX_REGFILE_0_INSTANCE
string "Core Instance Name" if ALLOW_EDIT_AUTO
default "opb_regfile_0"
config XILINX_REGFILE_0_HW_VER
string "Core version number" if ALLOW_EDIT_AUTO
default "1.00.a"
# Definitions for GPIO_0
comment "Definitions for GPIO_0"
depends on ALLOW_EDIT_AUTO
config XILINX_GPIO_0_INSTANCE
string "Core Instance Name" if ALLOW_EDIT_AUTO
default "Generic_GPIO"
config XILINX_GPIO_0_BASEADDR
hex "Base address" if ALLOW_EDIT_AUTO
default 0x20000000
config XILINX_GPIO_0_HIGHADDR
hex "High address" if ALLOW_EDIT_AUTO
default 0x2000FFFF
config XILINX_GPIO_0_USER_ID_CODE
int "USER_ID_CODE range (0:255)" if ALLOW_EDIT_AUTO
default 3
config XILINX_GPIO_0_OPB_AWIDTH
int "OPB_AWIDTH" if ALLOW_EDIT_AUTO
default 32
config XILINX_GPIO_0_OPB_DWIDTH
int "OPB_DWIDTH" if ALLOW_EDIT_AUTO
default 32
config XILINX_GPIO_0_FAMILY
string "Targetted FPGA family" if ALLOW_EDIT_AUTO
default "virtex5"
config XILINX_GPIO_0_GPIO_WIDTH
int "GPIO Data Width" if ALLOW_EDIT_AUTO
default 14
config XILINX_GPIO_0_ALL_INPUTS
int "Data pins are all inputs" if ALLOW_EDIT_AUTO
default 0
config XILINX_GPIO_0_INTERRUPT_PRESENT
int "INTERRUPT_PRESENT range (0,1)" if ALLOW_EDIT_AUTO
default 0
config XILINX_GPIO_0_IS_BIDIR
int "Data pins are bi-directional" if ALLOW_EDIT_AUTO
default 0
config XILINX_GPIO_0_DOUT_DEFAULT
hex "DOUT_DEFAULT" if ALLOW_EDIT_AUTO
default 0x00000000
config XILINX_GPIO_0_TRI_DEFAULT
hex "TRI_DEFAULT" if ALLOW_EDIT_AUTO
default 0xFFFFFFFF
config XILINX_GPIO_0_IS_DUAL
int "Use Dual GPIO" if ALLOW_EDIT_AUTO
default 0
config XILINX_GPIO_0_ALL_INPUTS_2
int "GPIO2 Data All Inputs" if ALLOW_EDIT_AUTO
default 0
config XILINX_GPIO_0_IS_BIDIR_2
int "Use GPIO2 Bidir IO Pin" if ALLOW_EDIT_AUTO
default 1
config XILINX_GPIO_0_DOUT_DEFAULT_2
hex "DOUT_DEFAULT_2" if ALLOW_EDIT_AUTO
default 0x00000000
config XILINX_GPIO_0_TRI_DEFAULT_2
hex "TRI_DEFAULT_2" if ALLOW_EDIT_AUTO
default 0xFFFFFFFF
config XILINX_GPIO_0_INSTANCE
string "Core Instance Name" if ALLOW_EDIT_AUTO
default "Generic_GPIO"
config XILINX_GPIO_0_HW_VER
string "Core version number" if ALLOW_EDIT_AUTO
default "3.01.b"
# Definitions for MCH_OPB_DDR_0
comment "Definitions for MCH_OPB_DDR_0"
depends on ALLOW_EDIT_AUTO
config XILINX_MCH_OPB_DDR_0_INSTANCE
string "Core Instance Name" if ALLOW_EDIT_AUTO
default "mch_opb_ddr_0"
config XILINX_MCH_OPB_DDR_0_FAMILY
string "Targetted FPGA family" if ALLOW_EDIT_AUTO
default "virtex5"
config XILINX_MCH_OPB_DDR_0_REG_DIMM
int "DDR device is a registerd DIMM" if ALLOW_EDIT_AUTO
default 0
config XILINX_MCH_OPB_DDR_0_NUM_BANKS_MEM
int "NUM_BANKS_MEM range (1:4)" if ALLOW_EDIT_AUTO
default 2
config XILINX_MCH_OPB_DDR_0_NUM_CLK_PAIRS
int "NUM_CLK_PAIRS range (1:4)" if ALLOW_EDIT_AUTO
default 2
config XILINX_MCH_OPB_DDR_0_DDR_ASYNC_SUPPORT
int "Separate DDR and bus clock domain" if ALLOW_EDIT_AUTO
default 1
config XILINX_MCH_OPB_DDR_0_EXTRA_TSU
int "EXTRA_TSU range (0:1)" if ALLOW_EDIT_AUTO
default 1
config XILINX_MCH_OPB_DDR_0_USE_OPEN_ROW_MNGT
int "USE_OPEN_ROW_MNGT range (0:1)" if ALLOW_EDIT_AUTO
default 1
config XILINX_MCH_OPB_DDR_0_INCLUDE_DDR_PIPE
int "INCLUDE_DDR_PIPE range (0:1)" if ALLOW_EDIT_AUTO
default 1
config XILINX_MCH_OPB_DDR_0_NUM_CHANNELS
int "NUM_CHANNELS range (1:4)" if ALLOW_EDIT_AUTO
default 2
config XILINX_MCH_OPB_DDR_0_PRIORITY_MODE
int "PRIORITY_MODE range (0)" if ALLOW_EDIT_AUTO
default 0
config XILINX_MCH_OPB_DDR_0_INCLUDE_OPB_IPIF
int "INCLUDE_OPB_IPIF range (0:1)" if ALLOW_EDIT_AUTO
default 1
config XILINX_MCH_OPB_DDR_0_INCLUDE_OPB_BURST_SUPPORT
int "Include Burst Transactions Support" if ALLOW_EDIT_AUTO
default 1
config XILINX_MCH_OPB_DDR_0_INCLUDE_TIMEOUT_CNTR
int "INCLUDE_TIMEOUT_CNTR range (0)" if ALLOW_EDIT_AUTO
default 0
config XILINX_MCH_OPB_DDR_0_TIMEOUT
int "TIMEOUT range (1:512)" if ALLOW_EDIT_AUTO
default 128
config XILINX_MCH_OPB_DDR_0_MCH_OPB_DWIDTH
int "MCH_OPB_DWIDTH" if ALLOW_EDIT_AUTO
default 32
config XILINX_MCH_OPB_DDR_0_MCH_OPB_AWIDTH
int "MCH_OPB_AWIDTH" if ALLOW_EDIT_AUTO
default 32
config XILINX_MCH_OPB_DDR_0_MCH_OPB_CLK_PERIOD_PS
int "MCH_OPB_CLK_PERIOD_PS" if ALLOW_EDIT_AUTO
default 16666
config XILINX_MCH_OPB_DDR_0_DDR_TMRD
int "DDR_TMRD" if ALLOW_EDIT_AUTO
default 15000
config XILINX_MCH_OPB_DDR_0_DDR_TWR
int "DDR_TWR" if ALLOW_EDIT_AUTO
default 15000
config XILINX_MCH_OPB_DDR_0_DDR_TWTR
int "DDR_TWTR" if ALLOW_EDIT_AUTO
default 1
config XILINX_MCH_OPB_DDR_0_DDR_TRAS
int "DDR_TRAS" if ALLOW_EDIT_AUTO
default 45000
config XILINX_MCH_OPB_DDR_0_DDR_TRC
int "DDR_TRC" if ALLOW_EDIT_AUTO
default 65000
config XILINX_MCH_OPB_DDR_0_DDR_TRFC
int "DDR_TRFC" if ALLOW_EDIT_AUTO
default 75000
config XILINX_MCH_OPB_DDR_0_DDR_TRCD
int "DDR_TRCD" if ALLOW_EDIT_AUTO
default 22500
config XILINX_MCH_OPB_DDR_0_DDR_TRRD
int "DDR_TRRD" if ALLOW_EDIT_AUTO
default 15000
config XILINX_MCH_OPB_DDR_0_DDR_TREFI
int "DDR_TREFI" if ALLOW_EDIT_AUTO
default 7800000
config XILINX_MCH_OPB_DDR_0_DDR_TRP
int "DDR_TRP" if ALLOW_EDIT_AUTO
default 22500
config XILINX_MCH_OPB_DDR_0_DDR_TXSR
int "DDR_TXSR" if ALLOW_EDIT_AUTO
default 200000
config XILINX_MCH_OPB_DDR_0_DDR_CAS_LAT
int "DDR_CAS_LAT range (2,3)" if ALLOW_EDIT_AUTO
default 3
config XILINX_MCH_OPB_DDR_0_DDR_DWIDTH
int "Data Width" if ALLOW_EDIT_AUTO
default 32
config XILINX_MCH_OPB_DDR_0_DDR_AWIDTH
int "Address Width" if ALLOW_EDIT_AUTO
default 13
config XILINX_MCH_OPB_DDR_0_DDR_COL_AWIDTH
int "Column Address Width" if ALLOW_EDIT_AUTO
default 9
config XILINX_MCH_OPB_DDR_0_DDR_BANK_AWIDTH
int "Bank Address Width" if ALLOW_EDIT_AUTO
default 2
config XILINX_MCH_OPB_DDR_0_MCH0_PROTOCOL
int "MCH0_PROTOCOL" if ALLOW_EDIT_AUTO
default 0
config XILINX_MCH_OPB_DDR_0_MCH0_ACCESSBUF_DEPTH
int "MCH0_ACCESSBUF_DEPTH range (4,8,16)" if ALLOW_EDIT_AUTO
default 16
config XILINX_MCH_OPB_DDR_0_MCH0_RDDATABUF_DEPTH
int "MCH0_RDDATABUF_DEPTH range (0,4,8,16)" if ALLOW_EDIT_AUTO
default 16
config XILINX_MCH_OPB_DDR_0_MCH1_PROTOCOL
int "MCH1_PROTOCOL" if ALLOW_EDIT_AUTO
default 0
config XILINX_MCH_OPB_DDR_0_MCH1_ACCESSBUF_DEPTH
int "MCH1_ACCESSBUF_DEPTH range (4,8,16)" if ALLOW_EDIT_AUTO
default 16
config XILINX_MCH_OPB_DDR_0_MCH1_RDDATABUF_DEPTH
int "MCH1_RDDATABUF_DEPTH range (0,4,8,16)" if ALLOW_EDIT_AUTO
default 16
config XILINX_MCH_OPB_DDR_0_MCH2_PROTOCOL
int "MCH2_PROTOCOL" if ALLOW_EDIT_AUTO
default 0
config XILINX_MCH_OPB_DDR_0_MCH2_ACCESSBUF_DEPTH
int "MCH2_ACCESSBUF_DEPTH range (4,8,16)" if ALLOW_EDIT_AUTO
default 16
config XILINX_MCH_OPB_DDR_0_MCH2_RDDATABUF_DEPTH
int "MCH2_RDDATABUF_DEPTH range (0,4,8,16)" if ALLOW_EDIT_AUTO
default 16
config XILINX_MCH_OPB_DDR_0_MCH3_PROTOCOL
int "MCH3_PROTOCOL" if ALLOW_EDIT_AUTO
default 0
config XILINX_MCH_OPB_DDR_0_MCH3_ACCESSBUF_DEPTH
int "MCH3_ACCESSBUF_DEPTH range (4,8,16)" if ALLOW_EDIT_AUTO
default 16
config XILINX_MCH_OPB_DDR_0_MCH3_RDDATABUF_DEPTH
int "MCH3_RDDATABUF_DEPTH range (0,4,8,16)" if ALLOW_EDIT_AUTO
default 16
config XILINX_MCH_OPB_DDR_0_XCL0_LINESIZE
int "XCL0_LINESIZE range (1,4,8,16)" if ALLOW_EDIT_AUTO
default 4
config XILINX_MCH_OPB_DDR_0_XCL0_WRITEXFER
int "XCL0_WRITEXFER range (0:2)" if ALLOW_EDIT_AUTO
default 1
config XILINX_MCH_OPB_DDR_0_XCL1_LINESIZE
int "XCL1_LINESIZE range (1,4,8,16)" if ALLOW_EDIT_AUTO
default 4
config XILINX_MCH_OPB_DDR_0_XCL1_WRITEXFER
int "XCL1_WRITEXFER range (0:2)" if ALLOW_EDIT_AUTO
default 1
config XILINX_MCH_OPB_DDR_0_XCL2_LINESIZE
int "XCL2_LINESIZE range (1,4,8,16)" if ALLOW_EDIT_AUTO
default 4
config XILINX_MCH_OPB_DDR_0_XCL2_WRITEXFER
int "XCL2_WRITEXFER range (0:2)" if ALLOW_EDIT_AUTO
default 1
config XILINX_MCH_OPB_DDR_0_XCL3_LINESIZE
int "XCL3_LINESIZE range (1,4,8,16)" if ALLOW_EDIT_AUTO
default 4
config XILINX_MCH_OPB_DDR_0_XCL3_WRITEXFER
int "XCL3_WRITEXFER range (0:2)" if ALLOW_EDIT_AUTO
default 1
config XILINX_MCH_OPB_DDR_0_MEM0_BASEADDR
hex "Bank 0 Base Address" if ALLOW_EDIT_AUTO
default 0x30000000
config XILINX_MCH_OPB_DDR_0_MEM0_HIGHADDR
hex "Bank 0 High Address" if ALLOW_EDIT_AUTO
default 0x37FFFFFF
config XILINX_MCH_OPB_DDR_0_MEM1_BASEADDR
hex "MEM1_BASEADDR" if ALLOW_EDIT_AUTO
default 0x38000000
config XILINX_MCH_OPB_DDR_0_MEM1_HIGHADDR
hex "MEM1_HIGHADDR" if ALLOW_EDIT_AUTO
default 0x3FFFFFFF
config XILINX_MCH_OPB_DDR_0_MEM2_BASEADDR
hex "MEM2_BASEADDR" if ALLOW_EDIT_AUTO
default 0xFFFFFFFF
config XILINX_MCH_OPB_DDR_0_MEM2_HIGHADDR
hex "MEM2_HIGHADDR" if ALLOW_EDIT_AUTO
default 0x00000000
config XILINX_MCH_OPB_DDR_0_MEM3_BASEADDR
hex "MEM3_BASEADDR" if ALLOW_EDIT_AUTO
default 0xFFFFFFFF
config XILINX_MCH_OPB_DDR_0_MEM3_HIGHADDR
hex "MEM3_HIGHADDR" if ALLOW_EDIT_AUTO
default 0x00000000
config XILINX_MCH_OPB_DDR_0_SIM_INIT_TIME_PS
int "SIM_INIT_TIME_PS" if ALLOW_EDIT_AUTO
default 200000000
config XILINX_MCH_OPB_DDR_0_INSTANCE
string "Core Instance Name" if ALLOW_EDIT_AUTO
default "mch_opb_ddr_0"
config XILINX_MCH_OPB_DDR_0_HW_VER
string "Core version number" if ALLOW_EDIT_AUTO
default "1.01.c"
# Definitions for MDM_0
comment "Definitions for MDM_0"
depends on ALLOW_EDIT_AUTO
config XILINX_MDM_0_INSTANCE
string "Core Instance Name" if ALLOW_EDIT_AUTO
default "opb_mdm_0"
config XILINX_MDM_0_BASEADDR
hex "Base address" if ALLOW_EDIT_AUTO
default 0x21400000
config XILINX_MDM_0_HIGHADDR
hex "High address" if ALLOW_EDIT_AUTO
default 0x2140FFFF
config XILINX_MDM_0_OPB_DWIDTH
int "OPB_DWIDTH" if ALLOW_EDIT_AUTO
default 32
config XILINX_MDM_0_OPB_AWIDTH
int "OPB_AWIDTH" if ALLOW_EDIT_AUTO
default 32
config XILINX_MDM_0_FAMILY
string "Targetted FPGA family" if ALLOW_EDIT_AUTO
default "virtex5"
config XILINX_MDM_0_MB_DBG_PORTS
int "MB_DBG_PORTS range (0:8)" if ALLOW_EDIT_AUTO
default 1
config XILINX_MDM_0_USE_UART
int "USE_UART range (0:1)" if ALLOW_EDIT_AUTO
default 1
config XILINX_MDM_0_UART_WIDTH
int "UART_WIDTH range (8,16,32)" if ALLOW_EDIT_AUTO
default 32
config XILINX_MDM_0_WRITE_FSL_PORTS
int "WRITE_FSL_PORTS range (0:1)" if ALLOW_EDIT_AUTO
default 0
config XILINX_MDM_0_INSTANCE
string "Core Instance Name" if ALLOW_EDIT_AUTO
default "opb_mdm_0"
config XILINX_MDM_0_HW_VER
string "Core version number" if ALLOW_EDIT_AUTO
default "2.00.a"
config XILINX_MDM_0_IRQ
int "IRQ number of MDM_0" if ALLOW_EDIT_AUTO
default 0
# Definitions for UARTLITE_0
comment "Definitions for UARTLITE_0"
depends on ALLOW_EDIT_AUTO
config XILINX_UARTLITE_0_INSTANCE
string "Core Instance Name" if ALLOW_EDIT_AUTO
default "RS232_Uart"
config XILINX_UARTLITE_0_BASEADDR
hex "Base address" if ALLOW_EDIT_AUTO
default 0x20400000
config XILINX_UARTLITE_0_HIGHADDR
hex "High address" if ALLOW_EDIT_AUTO
default 0x2040FFFF
config XILINX_UARTLITE_0_OPB_DWIDTH
int "OPB_DWIDTH" if ALLOW_EDIT_AUTO
default 32
config XILINX_UARTLITE_0_OPB_AWIDTH
int "OPB_AWIDTH" if ALLOW_EDIT_AUTO
default 32
config XILINX_UARTLITE_0_DATA_BITS
int "Num Data Bits" if ALLOW_EDIT_AUTO
default 8
config XILINX_UARTLITE_0_CLK_FREQ
int "CLK_FREQ" if ALLOW_EDIT_AUTO
default 60000000
config XILINX_UARTLITE_0_BAUDRATE
int "Baudrate" if ALLOW_EDIT_AUTO
default 115200
config XILINX_UARTLITE_0_USE_PARITY
int "Use Parity" if ALLOW_EDIT_AUTO
default 0
config XILINX_UARTLITE_0_ODD_PARITY
int "Parity Type" if ALLOW_EDIT_AUTO
default 0
config XILINX_UARTLITE_0_INSTANCE
string "Core Instance Name" if ALLOW_EDIT_AUTO
default "RS232_Uart"
config XILINX_UARTLITE_0_HW_VER
string "Core version number" if ALLOW_EDIT_AUTO
default "1.00.b"
config XILINX_UARTLITE_0_IRQ
int "IRQ number of UARTLITE_0" if ALLOW_EDIT_AUTO
default 3
# Definitions for TIMER_0
comment "Definitions for TIMER_0"
depends on ALLOW_EDIT_AUTO
config XILINX_TIMER_0_INSTANCE
string "Core Instance Name" if ALLOW_EDIT_AUTO
default "opb_timer_0"
config XILINX_TIMER_0_FAMILY
string "Targetted FPGA family" if ALLOW_EDIT_AUTO
default "virtex5"
config XILINX_TIMER_0_COUNT_WIDTH
int "Counter Bit Width" if ALLOW_EDIT_AUTO
default 32
config XILINX_TIMER_0_ONE_TIMER_ONLY
int "Timer Mode" if ALLOW_EDIT_AUTO
default 0
config XILINX_TIMER_0_TRIG0_ASSERT
int "TRIG0_ASSERT range (0,1)" if ALLOW_EDIT_AUTO
default 1
config XILINX_TIMER_0_TRIG1_ASSERT
int "TRIG1_ASSERT range (0,1)" if ALLOW_EDIT_AUTO
default 1
config XILINX_TIMER_0_GEN0_ASSERT
int "GEN0_ASSERT range (0,1)" if ALLOW_EDIT_AUTO
default 1
config XILINX_TIMER_0_GEN1_ASSERT
int "GEN1_ASSERT range (0,1)" if ALLOW_EDIT_AUTO
default 1
config XILINX_TIMER_0_OPB_AWIDTH
int "OPB_AWIDTH" if ALLOW_EDIT_AUTO
default 32
config XILINX_TIMER_0_OPB_DWIDTH
int "OPB_DWIDTH" if ALLOW_EDIT_AUTO
default 32
config XILINX_TIMER_0_BASEADDR
hex "Base address" if ALLOW_EDIT_AUTO
default 0x26000000
config XILINX_TIMER_0_HIGHADDR
hex "High address" if ALLOW_EDIT_AUTO
default 0x260000FF
config XILINX_TIMER_0_INSTANCE
string "Core Instance Name" if ALLOW_EDIT_AUTO
default "opb_timer_0"
config XILINX_TIMER_0_HW_VER
string "Core version number" if ALLOW_EDIT_AUTO
default "1.00.b"
config XILINX_TIMER_0_IRQ
int "IRQ number of TIMER_0" if ALLOW_EDIT_AUTO
default 1
# Definitions for INTC_0
comment "Definitions for INTC_0"
depends on ALLOW_EDIT_AUTO
config XILINX_INTC_0_INSTANCE
string "Core Instance Name" if ALLOW_EDIT_AUTO
default "opb_intc_0"
config XILINX_INTC_0_FAMILY
string "Targetted FPGA family" if ALLOW_EDIT_AUTO
default "virtex5"
config XILINX_INTC_0_Y
int "Y" if ALLOW_EDIT_AUTO
default 0
config XILINX_INTC_0_X
int "X" if ALLOW_EDIT_AUTO
default 0
config XILINX_INTC_0_U_SET
string "U_SET" if ALLOW_EDIT_AUTO
default "intc"
config XILINX_INTC_0_OPB_AWIDTH
int "OPB_AWIDTH" if ALLOW_EDIT_AUTO
default 32
config XILINX_INTC_0_OPB_DWIDTH
int "OPB_DWIDTH" if ALLOW_EDIT_AUTO
default 32
config XILINX_INTC_0_BASEADDR
hex "Base address" if ALLOW_EDIT_AUTO
default 0x27000000
config XILINX_INTC_0_HIGHADDR
hex "High address" if ALLOW_EDIT_AUTO
default 0x2700003F
config XILINX_INTC_0_NUM_INTR_INPUTS
int "NUM_INTR_INPUTS range (1:C_OPB_DWIDTH)" if ALLOW_EDIT_AUTO
default 4
config XILINX_INTC_0_KIND_OF_INTR
hex "KIND_OF_INTR" if ALLOW_EDIT_AUTO
default 0x00000009
config XILINX_INTC_0_KIND_OF_EDGE
hex "KIND_OF_EDGE" if ALLOW_EDIT_AUTO
default 0x00000009
config XILINX_INTC_0_KIND_OF_LVL
hex "KIND_OF_LVL" if ALLOW_EDIT_AUTO
default 0x00000006
config XILINX_INTC_0_HAS_IPR
int "Interrupt Pending Register" if ALLOW_EDIT_AUTO
default 1
config XILINX_INTC_0_HAS_SIE
int "Set Interrupt Enables" if ALLOW_EDIT_AUTO
default 1
config XILINX_INTC_0_HAS_CIE
int "Clear Interrupt Enables" if ALLOW_EDIT_AUTO
default 1
config XILINX_INTC_0_HAS_IVR
int "Interrupt Vector Register" if ALLOW_EDIT_AUTO
default 1
config XILINX_INTC_0_IRQ_IS_LEVEL
int "IRQ_IS_LEVEL range (0, 1)" if ALLOW_EDIT_AUTO
default 1
config XILINX_INTC_0_IRQ_ACTIVE
int "IRQ_ACTIVE range (0, 1)" if ALLOW_EDIT_AUTO
default 1
config XILINX_INTC_0_INSTANCE
string "Core Instance Name" if ALLOW_EDIT_AUTO
default "opb_intc_0"
config XILINX_INTC_0_HW_VER
string "Core version number" if ALLOW_EDIT_AUTO
default "1.00.c"
# Peripheral counts
comment "Peripheral counts"
depends on ALLOW_EDIT_AUTO
config XILINX_GPIF2OPB_MASTER_NOFIFO_NUM_INSTANCES
int "Number of GPIF2OPB_MASTER_NOFIFO instances" if
ALLOW_EDIT_AUTO
default 1
config XILINX_V20_NUM_INSTANCES
int "Number of V20 instances" if ALLOW_EDIT_AUTO
default 1
config XILINX_LMB_BRAM_IF_CNTLR_NUM_INSTANCES
int "Number of LMB_BRAM_IF_CNTLR instances" if ALLOW_EDIT_AUTO
default 2
config XILINX_TIMER_NUM_INSTANCES
int "Number of TIMER instances" if ALLOW_EDIT_AUTO
default 1
config XILINX_MCH_OPB_DDR_NUM_INSTANCES
int "Number of MCH_OPB_DDR instances" if ALLOW_EDIT_AUTO
default 1
config XILINX_INTC_NUM_INSTANCES
int "Number of INTC instances" if ALLOW_EDIT_AUTO
default 1
config XILINX_UARTLITE_NUM_INSTANCES
int "Number of UARTLITE instances" if ALLOW_EDIT_AUTO
default 1
config XILINX_MDM_NUM_INSTANCES
int "Number of MDM instances" if ALLOW_EDIT_AUTO
default 1
config XILINX_REGFILE_NUM_INSTANCES
int "Number of REGFILE instances" if ALLOW_EDIT_AUTO
default 1
config XILINX_GPIO_NUM_INSTANCES
int "Number of GPIO instances" if ALLOW_EDIT_AUTO
default 1
config XILINX_IP_OPB2PIO_NUM_INSTANCES
int "Number of IP_OPB2PIO instances" if ALLOW_EDIT_AUTO
default 1
-----Original Message-----
From: owner-microblaze-uclinux@xxxxxxxxxxxxxx
[mailto:owner-microblaze-uclinux@xxxxxxxxxxxxxx] On Behalf Of Michal
Simek
Sent: Monday, April 21, 2008 10:48 PM
To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: [microblaze-uclinux] RE: [microblaze-uclinux] [uClinux-dev]
problems downloading image.bin for kernel 2.6
Hi Ken,
I think you must send .config and Kconfig.auto file for simple analyze
your problem.
If you have reference board you can try it. I hope that these HW design
and kernels works well.
If you use U-BOOT for downloading kernel you can see output buffer.
cat System.map | grep __log_buf. You can do it from xmd too but you
can't see output in text (only hex values).
Michal Simek
John,
Went to Device Drivers -> Character Devices -> Serial Devices
-->
8250/16550 (un-checked)
Xilinx uartlite Serial port support (checked)
Support for console on Xilinx uartlite serial port (checked)
It did not fix the problem. Trying to place break points to figure out
where it goes.
Ken
-----Original Message-----
From: owner-microblaze-uclinux@xxxxxxxxxxxxxx
[mailto:owner-microblaze-uclinux@xxxxxxxxxxxxxx] On Behalf Of John
Williams
Sent: Monday, April 21, 2008 3:06 PM
To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: Re: [microblaze-uclinux] [uClinux-dev] problems downloading
image.bin for kernel 2.6
Hi Ken,
Kenneth Schultz wrote:
> I am getting this same error on uBlaze. I also see some patches on
the
> a kernel when I Google this. Do we need a patch to fix this?
In kernel menuconfig, drivers - > serial, make sure "uartlite driver"
and "console on uartlite" are both selected. These should be selected
by default, but are not in the current release. It's fixed in our tree
ready for next release.
Regards,
John
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Mailing List Archive :
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___________________________
microblaze-uclinux mailing list
microblaze-uclinux@xxxxxxxxxxxxxx
Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
Mailing List Archive :
http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
___________________________
microblaze-uclinux mailing list
microblaze-uclinux@xxxxxxxxxxxxxx
Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
Mailing List Archive :
http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
___________________________
microblaze-uclinux mailing list
microblaze-uclinux@xxxxxxxxxxxxxx
Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/