Hi Sebastian,
I don't see any reasons why you can't simulate the complete design including the processor. If you want to simulate only your IP, you need to build up a test bench or do force testing which could be painful depending on the design complexity.
The best way to go forward is to generate a simulation model of the whole system using XPS. Modelsim is launched directly and you don't need to create a test bench. This way you can test your software running on the processor also.
While testing, the whole system, if you change your software then you have to recompile the software in EDK and launch the modelsim again. If you do some modification in your custom logic, you just need to recompile that module in Modelsim (re-synthesis is not required for simulation).
Regards,
Sunil
-----Original Message-----
From: owner-microblaze-uclinux@xxxxxxxxxxxxxx on behalf of John Williams
Sent: Fri 5/9/2008 12:39 PM
To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: Re: [microblaze-uclinux] simulate my design
Hi Sebstien,
Sebastian wrote:
i've got a strange problem with my user logic. but to debug this, i
cannot use try-and-error every time
because it takes so much time to compile and synthesize the whole design.
so i got the idea to simulate my design - but i don't know if this is
possible.
can i simulate only my ip logic or also simulate the complete system? i
cannot imagine how that would work.
would anybody be so kind and help me with some hints or document-links
how to achieve this?
i'm using xilinx edk and ise 9.1.
You have a few options - you can use the BFM (Bus Functional Model)
toolkit from IBM, with Xilinx tools and Model Sim, to simulate just the
interesting bits of your design.
e.g. for a PLB device, you would just instantiate a bus and your IP,
then write a little BFM script that initiates transactions on the bus.
Just search xilinx.com for BFM, you'll find some appnotes etc.
The ISE simulator is ... functional, although I've seen it do some
pretty wierd things in my tests with it.
I'm not sure if you can use BFM with ISE simulator - has anybody tried?
If you can't you have to roll your own testbenches. You'll want to
create minimal test systems rather than the entire CPU and peripheral
subsystems.
That's fine if it's using FSL or something simple like that, but
creating your own PLB driver in simulation just to test your core is a
pain (which is what's so nice about BFM).
If you have external interfaces to worry about, or memories, then it
just keeps getting more complex still...
There's a reason why verification can be 70-90% of total costs for
serious chip designers!
Cheers,
John
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