[microblaze-uclinux] MPCM with SDRAM and cache issues

[Florian Fainelli <florian.fainelli@xxxxxxxxxxxxxxx>]

Hi all,

I am currently validating a hardware design using Xilinx EDK 10.1.02, my MPMC 
configuration is as follows :

- port 1 (XCL) is connected to the Data cache of the Microblaze instance, with 
writethrough enabled
- port 2 (XCL) is conneced to the Instruction cache
- port 3 is PLB v4.6
- DCM is configured appropriately to output the needed clocks (with phasing)

Both caches are 8KB. Now the following configurations have been tested :

- SDRAM clocked at 100 Mhz, PLB at 50 Mhz with caches crashes randomly
- SDRAM clocked at 100 Mhz, PLB at 50 Mhz without caches seems to work better, 
but not that well
- SDRAM clocked at 50 Mhz, PLB at 50 Mhz without caches works fine

What I will be testing soon is clocking the PLB at 25 Mhz and the SDRAM at 50 
Mhz w/ and w/o caches enabled. 

Are there any known issues with caches and SDRAM frequency, is the SDRAM/MPMC 
couple correctly maintainted ? My main concern is to make sure my design is 
not defective, but that this is HDL issue.

Thank you very much in advance for your answer/hints
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