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I believe that I could just use
a Xilinx MPMC xps core with 2 ports to my 1 physical RAM chip. I did not know
that the Xilinx MPMC xps core had arbitration built into it. But I am still open to other suggestions. -A Bose From:
owner-microblaze-uclinux@xxxxxxxxxxxxxx
[mailto:owner-microblaze-uclinux@xxxxxxxxxxxxxx] On Behalf Of A. Bose Hello, I have an EDK design that requires the use of the V5 Hard
Ethernet MAC. I only have 1 RAM chip. Initially I was thinking I could just use
the lltemac core along with the llfifo to connect it to the xps bus (petalinux).
Now just looking at the lltemac petalinux driver it seems that I need a
dedicated piece of RAM for the Ethernet traffic (lltemac to connect to the
local link to the mpmc controller). Then the petalinux lltemac driver controls
the mpmc and the lltemac cores. But since I have only 1 single port RAM chip I
am short because petalinux requires RAM as well. -I could “divide” my RAM into two distinct
parts, but I would have to arbitrate the read and write signals, not a very
clean solution. -I have no experience with linux kernel space, but how bad
would it be to modify the temac driver to handle data from the llfifo instead
of the mpmc interface? -I thought of creating a BRAM wrapper/pcore with local link
and mpmc interfaces, that way the lltemac would connect to it (I don’t
need large ethernet buffering, as they are just control packets) and the
petalinux driver would have the interfaces it requires, but it doesn’
seem too clean either. Any other suggestions? Thanks in advance for any help, -A Bose Internal Virus Database is out-of-date. Internal Virus Database is out-of-date. Internal Virus Database is out-of-date. |