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Re: [microblaze-uclinux] Petalinux with EDK 10.1

To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: Re: [microblaze-uclinux] Petalinux with EDK 10.1
From: Michal Simek <monstr@xxxxxxxxx>
Date: Tue, 21 Oct 2008 09:15:22 +0200
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Hi Jim,

you use any older petalinux version. You are right in newest Microblaze CPU
(from EDK10.1) is changed clock handling. Parameter which rewrite is set as
deprecated. For correct behavior please update petalinux bsp in
hardware/edk_user_repository from svn repo. There is fixed this issue.

Thanks,
Michal


> Hi all,
> 
> .... just to summarize what I think I got from this thread and looking
> at my project.
> 
> 1. Adding the line PARAMETER CORE_CLOCK_FREQ_HZ = 100000000 (or whatever
> your frequency is) to the mss file totally fixes the missing deprecated
> parameter issue.
> 
> 2. When I had a look at the SYS_Rst port on the fsl bus in my 10.1
> project, I saw that it was unconnected.  All the other buses are
> connected to the active-high reset signal "sys_bus_reset".  Making the
> FSL bus need an active low reset didn't make any sense to me, so I
> connected the SYS_Rst port to the sys_bus_reset signal and kept the
> "External Reset Active High" checkbox for the fsl_v20_0 bus checked. 
> The only active low reset in the system seems to be the raw external
> reset from FPGA pin sys_rst_s.  Is this thread saying that I should
> connect and use this signal for the fsl bus?
> 
> Does anyone know of any other 10.1-related issues that might arise in
> getting the hardware settings successfully out of the Xilinx tools and
> into Petalinux?  Any incompatibilities in the latest cores that I should
> stay away from?  Just installed the latest service packs from Xilinx:
> ISE 10.1.03 / EDK 10.1.03.
> 
> I've attached the mhs from my project, for reference:
> 
> Thanks,
> 
> Jim
> 
> 
> #
> ##############################################################################
> 
> # Created by Base System Builder Wizard for Xilinx EDK 10.1.02 Build
> EDK_K_SP2.5
> # Tue Sep 23 14:09:20 2008
> # Target Board:  Custom
> # Family:    spartan3
> # Device:    xc3s4000
> # Package:   fg676
> # Speed Grade:  -5
> # Processor: microblaze_0
> # System clock frequency: 66.00 MHz
> # On Chip Memory :  16 KB
> #
> ##############################################################################
> 
> PARAMETER VERSION = 2.1.0
> 
> 
> PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 132000000
> PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
> PORT fpga_0_Generic_GPIO_GPIO_d_out_pin =
> fpga_0_Generic_GPIO_GPIO_d_out, DIR = O, VEC = [0:3]
> PORT fpga_0_Generic_GPIO_GPIO_in_pin = fpga_0_Generic_GPIO_GPIO_in, DIR
> = I, VEC = [0:3]
> PORT fpga_0_Generic_GPIO_GPIO_t_out_pin =
> fpga_0_Generic_GPIO_GPIO_t_out, DIR = O, VEC = [0:3]
> PORT fpga_0_Generic_GPIO_GPIO_IO_pin = fpga_0_Generic_GPIO_GPIO_IO, DIR
> = IO, VEC = [0:3]
> PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = I
> PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = O
> PORT PIC_RX_port = PIC_RX, DIR = I
> PORT PIC_TX_port = PIC_TX, DIR = O
> PORT DDR_Clk_port = DDR_Clk, DIR = O, VEC = [1:0]
> PORT DDR_Clk_n_port = DDR_Clk_n, DIR = O, VEC = [1:0]
> PORT DDR_Addr_port = DDR_Addr, DIR = O, VEC = [12:0]
> PORT DDR_BankAddr_port = DDR_BankAddr, DIR = O, VEC = [1:0]
> PORT DDR_CAS_n_port = DDR_CAS_n, DIR = O
> PORT DDR_CE_port = DDR_CE, DIR = O
> PORT DDR_CS_n_port = DDR_CS_n, DIR = O
> PORT DDR_RAS_n_port = DDR_RAS_n, DIR = O
> PORT DDR_WE_n_port = DDR_WE_n, DIR = O
> PORT DDR_DM_port = DDR_DM, DIR = O, VEC = [3:0]
> PORT DDR_DQS = DDR_DQS, DIR = IO, VEC = [3:0]
> PORT DDR_DQ = DDR_DQ, DIR = IO, VEC = [31:0]
> PORT SysACE_CLK_port = SysACE_CLK, DIR = I
> PORT SysACE_clk_enable_n_port = net_gnd, DIR = O
> PORT SysACE_MPA_port = SysACE_MPA, DIR = O, VEC = [6:0]
> PORT SysACE_MPD_port = SysACE_MPD, DIR = IO, VEC = [15:0]
> PORT SysACE_CEN_port = SysACE_CEN, DIR = O
> PORT SysACE_OEN_port = SysACE_OEN, DIR = O
> PORT SysACE_WEN_port = SysACE_WEN, DIR = O
> PORT SysACE_MPIRQ_port = SysACE_MPIRQ, DIR = I
> PORT ETH_PHY_tx_data_port = ETH_PHY_tx_data, DIR = O, VEC = [3:0]
> PORT ETH_PHY_tx_en_port = ETH_PHY_tx_en, DIR = O
> PORT ETH_PHY_rst_n_port = ETH_PHY_rst_n, DIR = O
> PORT ETH_PHY_rx_er_port = ETH_PHY_rx_er, DIR = I
> PORT ETH_PHY_col_port = ETH_PHY_col, DIR = I
> PORT ETH_PHY_rx_data_port = ETH_PHY_rx_data, DIR = I, VEC = [3:0]
> PORT ETH_PHY_dv_port = ETH_PHY_dv, DIR = I
> PORT ETH_PHY_crs_port = ETH_PHY_crs, DIR = I
> PORT ETH_PHY_rx_clk_port = ETH_PHY_rx_clk, DIR = I
> PORT ETH_PHY_tx_clk_port = ETH_PHY_tx_clk, DIR = I
> PORT usb_ft245_USB_siwu_port = usb_ft245_USB_siwu, DIR = O
> PORT usb_ft245_USB_pwren_n_port = usb_ft245_USB_pwren_n, DIR = I
> PORT usb_ft245_USB_reset_n_port = usb_ft245_USB_reset_n, DIR = O
> PORT usb_ft245_USB_connected_port = usb_ft245_USB_connected, DIR = I
> PORT usb_ft245_USB_rxf_n_port = usb_ft245_USB_rxf_n, DIR = I
> PORT usb_ft245_USB_txe_n_port = usb_ft245_USB_txe_n, DIR = I
> PORT usb_ft245_USB_wr_port = usb_ft245_USB_wr, DIR = O
> PORT usb_ft245_USB_rd_n_port = usb_ft245_USB_rd_n, DIR = O
> PORT usb_ft245_USB_data = usb_ft245_USB_data, DIR = IO, VEC = [7:0]
> PORT usb_vnc1l_USB_dataack_n_port = usb_vnc1l_USB_dataack_n, DIR = I
> PORT usb_vnc1l_USB_datareq_n_port = usb_vnc1l_USB_datareq_n, DIR = O
> PORT usb_vnc1l_USB_busflag_port = usb_vnc1l_USB_busflag, DIR = I
> PORT usb_vnc1l_USB_poweren_port = usb_vnc1l_USB_poweren, DIR = O
> PORT usb_vnc1l_USB_reset_n_port = usb_vnc1l_USB_reset_n, DIR = O
> PORT usb_vnc1l_USB_rxf_n_port = usb_vnc1l_USB_rxf_n, DIR = I
> PORT usb_vnc1l_USB_txe_n_port = usb_vnc1l_USB_txe_n, DIR = I
> PORT usb_vnc1l_USB_wr_port = usb_vnc1l_USB_wr, DIR = O
> PORT usb_vnc1l_USB_rd_n_port = usb_vnc1l_USB_rd_n, DIR = O
> PORT usb_vnc1l_USB_data = usb_vnc1l_USB_data, DIR = IO, VEC = [7:0]
> PORT gpio_ds3231_GPIO_IO = gpio_ds3231_GPIO_IO, DIR = IO, VEC = [0:3]
> PORT gpio_OW_GPIO_IO = gpio_OW_GPIO_IO, DIR = IO, VEC = [0:0]
> 
> 
> BEGIN microblaze
> PARAMETER INSTANCE = microblaze_0
> PARAMETER HW_VER = 7.10.c
> PARAMETER C_USE_ICACHE = 1
> PARAMETER C_CACHE_BYTE_SIZE = 16384
> PARAMETER C_USE_DCACHE = 1
> PARAMETER C_DCACHE_BYTE_SIZE = 16384
> PARAMETER C_DEBUG_ENABLED = 1
> PARAMETER C_ICACHE_BASEADDR = 0x88000000
> PARAMETER C_ICACHE_HIGHADDR = 0x8bffffff
> PARAMETER C_DCACHE_BASEADDR = 0x88000000
> PARAMETER C_DCACHE_HIGHADDR = 0x8bffffff
> PARAMETER C_AREA_OPTIMIZED = 1
> PARAMETER C_USE_BARREL = 1
> PARAMETER C_FSL_LINKS = 1
> PARAMETER C_FAMILY = spartan3
> PARAMETER C_INSTANCE = microblaze_0
> BUS_INTERFACE DPLB = mb_plb
> BUS_INTERFACE IPLB = mb_plb
> BUS_INTERFACE ixcl = ixcl
> BUS_INTERFACE dxcl = dxcl
> BUS_INTERFACE DEBUG = microblaze_0_dbg
> BUS_INTERFACE DLMB = dlmb
> BUS_INTERFACE ILMB = ilmb
> BUS_INTERFACE SFSL0 = fsl_v20_0
> PORT MB_RESET = mb_reset
> PORT Interrupt = Interrupt
> END
> 
> BEGIN fsl_v20
> PARAMETER INSTANCE = fsl_v20_0
> PARAMETER HW_VER = 2.11.a
> PORT FSL_Clk = sys_clk_s
> END
> 
> BEGIN plb_v46
> PARAMETER INSTANCE = mb_plb
> PARAMETER HW_VER = 1.03.a
> PORT PLB_Clk = sys_clk_s
> PORT SYS_Rst = sys_bus_reset
> END
> 
> BEGIN lmb_v10
> PARAMETER INSTANCE = ilmb
> PARAMETER HW_VER = 1.00.a
> PORT LMB_Clk = sys_clk_s
> PORT SYS_Rst = sys_bus_reset
> END
> 
> BEGIN lmb_v10
> PARAMETER INSTANCE = dlmb
> PARAMETER HW_VER = 1.00.a
> PORT LMB_Clk = sys_clk_s
> PORT SYS_Rst = sys_bus_reset
> END
> 
> BEGIN lmb_bram_if_cntlr
> PARAMETER INSTANCE = dlmb_cntlr
> PARAMETER HW_VER = 2.10.a
> PARAMETER C_BASEADDR = 0x00000000
> PARAMETER C_HIGHADDR = 0x00003fff
> BUS_INTERFACE SLMB = dlmb
> BUS_INTERFACE BRAM_PORT = dlmb_port
> END
> 
> BEGIN lmb_bram_if_cntlr
> PARAMETER INSTANCE = ilmb_cntlr
> PARAMETER HW_VER = 2.10.a
> PARAMETER C_BASEADDR = 0x00000000
> PARAMETER C_HIGHADDR = 0x00003fff
> BUS_INTERFACE SLMB = ilmb
> BUS_INTERFACE BRAM_PORT = ilmb_port
> END
> 
> BEGIN bram_block
> PARAMETER INSTANCE = lmb_bram
> PARAMETER HW_VER = 1.00.a
> BUS_INTERFACE PORTA = ilmb_port
> BUS_INTERFACE PORTB = dlmb_port
> END
> 
> BEGIN xps_uartlite
> PARAMETER INSTANCE = RS232
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_BAUDRATE = 38400
> PARAMETER C_DATA_BITS = 8
> PARAMETER C_ODD_PARITY = 1
> PARAMETER C_USE_PARITY = 0
> PARAMETER C_SPLB_CLK_FREQ_HZ = 66000000
> PARAMETER C_BASEADDR = 0x84020000
> PARAMETER C_HIGHADDR = 0x8402ffff
> BUS_INTERFACE SPLB = mb_plb
> PORT RX = fpga_0_RS232_RX
> PORT TX = fpga_0_RS232_TX
> PORT Interrupt = RS232_Interrupt
> END
> 
> BEGIN xps_gpio
> PARAMETER INSTANCE = Generic_GPIO
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_ALL_INPUTS = 0
> PARAMETER C_GPIO_WIDTH = 4
> PARAMETER C_IS_BIDIR = 0
> PARAMETER C_IS_DUAL = 0
> PARAMETER C_BASEADDR = 0x81420000
> PARAMETER C_HIGHADDR = 0x8142ffff
> BUS_INTERFACE SPLB = mb_plb
> PORT GPIO_d_out = fpga_0_Generic_GPIO_GPIO_d_out
> PORT GPIO_in = fpga_0_Generic_GPIO_GPIO_in
> PORT GPIO_t_out = fpga_0_Generic_GPIO_GPIO_t_out
> PORT GPIO_IO = fpga_0_Generic_GPIO_GPIO_IO
> END
> 
> BEGIN xps_timer
> PARAMETER INSTANCE = xps_timer_1
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_COUNT_WIDTH = 32
> PARAMETER C_ONE_TIMER_ONLY = 1
> PARAMETER C_BASEADDR = 0x83c20000
> PARAMETER C_HIGHADDR = 0x83c2ffff
> BUS_INTERFACE SPLB = mb_plb
> PORT Interrupt = xps_timer_1_Interrupt
> END
> 
> BEGIN mdm
> PARAMETER INSTANCE = debug_module
> PARAMETER HW_VER = 1.00.c
> PARAMETER C_MB_DBG_PORTS = 1
> PARAMETER C_USE_UART = 1
> PARAMETER C_UART_WIDTH = 8
> PARAMETER C_BASEADDR = 0x84400000
> PARAMETER C_HIGHADDR = 0x8440ffff
> BUS_INTERFACE SPLB = mb_plb
> BUS_INTERFACE MBDEBUG_0 = microblaze_0_dbg
> BUS_INTERFACE MFSL0 = fsl_v20_0
> PORT Debug_SYS_Rst = Debug_SYS_Rst
> PORT Interrupt = debug_IRQ
> END
> 
> BEGIN proc_sys_reset
> PARAMETER INSTANCE = proc_sys_reset_0
> PARAMETER HW_VER = 2.00.a
> PARAMETER C_EXT_RESET_HIGH = 0
> PORT Slowest_sync_clk = sys_clk_s
> PORT Dcm_locked = Dcm_all_locked
> PORT Ext_Reset_In = sys_rst_s
> PORT MB_Reset = mb_reset
> PORT Bus_Struct_Reset = sys_bus_reset
> PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
> PORT Peripheral_Reset = sys_periph_reset
> END
> 
> BEGIN xps_intc
> PARAMETER INSTANCE = xps_intc_0
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_BASEADDR = 0x81800000
> PARAMETER C_HIGHADDR = 0x8180ffff
> BUS_INTERFACE SPLB = mb_plb
> PORT Irq = Interrupt
> PORT Intr =
> xps_timer_1_Interrupt&PIC_IRQ&RS232_Interrupt&SysACE_IRQ&debug_IRQ&xps_timer_0_Interrupt&usb_ft245_USB_int&usb_vnc1l_USB_int&ETH_IRQ
> 
> END
> 
> BEGIN mpmc
> PARAMETER INSTANCE = DDR
> PARAMETER HW_VER = 4.02.a
> PARAMETER C_NUM_PORTS = 3
> PARAMETER C_PIM0_BASETYPE = 1
> PARAMETER C_PIM1_BASETYPE = 1
> PARAMETER C_MEM_PARTNO = MT46V16M16-5B
> PARAMETER C_MEM_DATA_WIDTH = 32
> PARAMETER C_MEM_TYPE = DDR
> PARAMETER C_XCL0_WRITEXFER = 0
> PARAMETER C_PIM2_BASETYPE = 2
> PARAMETER C_MPMC_CLK0_PERIOD_PS = 7575
> PARAMETER C_USE_STATIC_PHY = 1
> PARAMETER C_MEM_CLK_WIDTH = 2
> PARAMETER C_STATIC_PHY_RDDATA_SWAP_RISE = 1
> PARAMETER C_STATIC_PHY_RDEN_DELAY = 6
> PARAMETER C_MPMC_BASEADDR = 0x88000000
> PARAMETER C_MPMC_HIGHADDR = 0x8fffffff
> PARAMETER C_MPMC_CTRL_BASEADDR = 0x84800000
> PARAMETER C_MPMC_CTRL_HIGHADDR = 0x8480ffff
> BUS_INTERFACE XCL0 = ixcl
> BUS_INTERFACE XCL1 = dxcl
> BUS_INTERFACE SPLB2 = mb_plb
> BUS_INTERFACE MPMC_CTRL = mb_plb
> PORT DDR_Addr = DDR_Addr
> PORT DDR_BankAddr = DDR_BankAddr
> PORT DDR_CAS_n = DDR_CAS_n
> PORT DDR_CE = DDR_CE
> PORT DDR_CS_n = DDR_CS_n
> PORT DDR_RAS_n = DDR_RAS_n
> PORT DDR_WE_n = DDR_WE_n
> PORT DDR_DM = DDR_DM
> PORT DDR_DQS = DDR_DQS
> PORT DDR_DQ = DDR_DQ
> PORT DDR_Clk = DDR_Clk
> PORT DDR_Clk_n = DDR_Clk_n
> # PORT DDR_DQS_Div_I = DDR_DQS_Div_I
> # PORT DDR_DQS_Div_O = DDR_DQS_Div_O
> PORT MPMC_Clk0 = DDR_mpmc_clk_s
> PORT MPMC_Clk90 = DDR_mpmc_clk_90_s
> PORT MPMC_Rst = sys_periph_reset
> PORT MPMC_Clk_Mem = DDR_mpmc_mem_clk_s
> PORT MPMC_DCM_PSEN = MPMC_PSEN
> PORT MPMC_DCM_PSINCDEC = MPMC_PSINCDEC
> PORT MPMC_DCM_PSDONE = MPMC_PSDONE
> END
> 
> BEGIN dcm_module
> PARAMETER INSTANCE = dcm_0
> PARAMETER HW_VER = 1.00.d
> PARAMETER C_CLK0_BUF = TRUE
> PARAMETER C_CLK90_BUF = TRUE
> PARAMETER C_CLKDV_BUF = TRUE
> PARAMETER C_CLKDV_DIVIDE = 2.0
> PARAMETER C_CLKIN_PERIOD = 7.576
> PARAMETER C_CLK_FEEDBACK = 1X
> PARAMETER C_DLL_FREQUENCY_MODE = LOW
> PARAMETER C_EXT_RESET_HIGH = 1
> PARAMETER C_CLKIN_DIVIDE_BY_2 = FALSE
> PORT CLKIN = dcm_clk_s
> PORT CLKDV = sys_clk_s
> PORT CLK0 = DDR_mpmc_clk_s
> PORT CLK90 = DDR_mpmc_clk_90_s
> PORT CLKFB = DDR_mpmc_clk_s
> PORT RST = net_gnd
> PORT LOCKED = dcm_0_lock
> END
> 
> BEGIN dcm_module
> PARAMETER INSTANCE = dcm_2
> PARAMETER HW_VER = 1.00.d
> PARAMETER C_CLK0_BUF = TRUE
> PARAMETER C_CLK90_BUF = FALSE
> PARAMETER C_CLKIN_PERIOD = 7.576
> PARAMETER C_CLK_FEEDBACK = 1X
> PARAMETER C_DLL_FREQUENCY_MODE = LOW
> PARAMETER C_EXT_RESET_HIGH = 0
> PARAMETER C_CLKOUT_PHASE_SHIFT = VARIABLE
> PARAMETER C_PHASE_SHIFT = -34
> # allowable phase shift range -168 to +168
> PORT CLKIN = DDR_mpmc_clk_s
> PORT CLK0 = DDR_mpmc_mem_clk_s
> PORT CLKFB = DDR_mpmc_mem_clk_s
> PORT RST = dcm_0_lock
> PORT PSEN = MPMC_PSEN
> PORT PSINCDEC = MPMC_PSINCDEC
> PORT PSCLK = DDR_mpmc_clk_s
> PORT PSDONE = MPMC_PSDONE
> PORT LOCKED = Dcm_all_locked
> END
> 
> BEGIN xps_sysace
> PARAMETER INSTANCE = SysACE
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_MEM_WIDTH = 16
> PARAMETER C_BASEADDR = 0x83600000
> PARAMETER C_HIGHADDR = 0x8360ffff
> BUS_INTERFACE SPLB = mb_plb
> PORT SysACE_CLK = SysACE_CLK
> PORT SysACE_MPA = SysACE_MPA
> PORT SysACE_MPD = SysACE_MPD
> PORT SysACE_CEN = SysACE_CEN
> PORT SysACE_OEN = SysACE_OEN
> PORT SysACE_WEN = SysACE_WEN
> PORT SysACE_MPIRQ = SysACE_MPIRQ
> PORT SysACE_IRQ = SysACE_IRQ
> END
> 
> BEGIN xps_uartlite
> PARAMETER INSTANCE = PIC
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_BAUDRATE = 38400
> PARAMETER C_DATA_BITS = 8
> PARAMETER C_ODD_PARITY = 1
> PARAMETER C_USE_PARITY = 0
> PARAMETER C_SPLB_CLK_FREQ_HZ = 66000000
> PARAMETER C_BASEADDR = 0x84000000
> PARAMETER C_HIGHADDR = 0x8400ffff
> BUS_INTERFACE SPLB = mb_plb
> PORT RX = PIC_RX
> PORT TX = PIC_TX
> PORT Interrupt = PIC_IRQ
> END
> 
> BEGIN xps_ethernetlite
> PARAMETER INSTANCE = xps_ethernetlite_0
> PARAMETER HW_VER = 2.00.a
> PARAMETER C_BASEADDR = 0x81000000
> PARAMETER C_HIGHADDR = 0x8100ffff
> BUS_INTERFACE SPLB = mb_plb
> PORT IP2INTC_Irpt = ETH_IRQ
> PORT PHY_tx_data = ETH_PHY_tx_data
> PORT PHY_tx_en = ETH_PHY_tx_en
> PORT PHY_rst_n = ETH_PHY_rst_n
> PORT PHY_rx_er = ETH_PHY_rx_er
> PORT PHY_col = ETH_PHY_col
> PORT PHY_rx_data = ETH_PHY_rx_data
> PORT PHY_dv = ETH_PHY_dv
> PORT PHY_crs = ETH_PHY_crs
> PORT PHY_rx_clk = ETH_PHY_rx_clk
> PORT PHY_tx_clk = ETH_PHY_tx_clk
> END
> 
> BEGIN plb_ftdi_usb
> PARAMETER INSTANCE = usb_vnc1l
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_BASEADDR = 0xc8200000
> PARAMETER C_HIGHADDR = 0xc820ffff
> BUS_INTERFACE SPLB = mb_plb
> PORT USB_int = usb_vnc1l_USB_int
> PORT USB_dataack_n = usb_vnc1l_USB_dataack_n
> PORT USB_datareq_n = usb_vnc1l_USB_datareq_n
> PORT USB_busflag = usb_vnc1l_USB_busflag
> PORT USB_poweren = usb_vnc1l_USB_poweren
> PORT USB_reset_n = usb_vnc1l_USB_reset_n
> PORT USB_rxf_n = usb_vnc1l_USB_rxf_n
> PORT USB_txe_n = usb_vnc1l_USB_txe_n
> PORT USB_wr = usb_vnc1l_USB_wr
> PORT USB_rd_n = usb_vnc1l_USB_rd_n
> PORT USB_data = usb_vnc1l_USB_data
> END
> 
> BEGIN plb_ftdi_usb
> PARAMETER INSTANCE = usb_ft245
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_BASEADDR = 0xc8220000
> PARAMETER C_HIGHADDR = 0xc822ffff
> BUS_INTERFACE SPLB = mb_plb
> PORT USB_int = usb_ft245_USB_int
> PORT USB_siwu = usb_ft245_USB_siwu
> PORT USB_pwren_n = usb_ft245_USB_pwren_n
> PORT USB_reset_n = usb_ft245_USB_reset_n
> PORT USB_connected = usb_ft245_USB_connected
> PORT USB_rxf_n = usb_ft245_USB_rxf_n
> PORT USB_txe_n = usb_ft245_USB_txe_n
> PORT USB_wr = usb_ft245_USB_wr
> PORT USB_rd_n = usb_ft245_USB_rd_n
> PORT USB_data = usb_ft245_USB_data
> END
> 
> BEGIN xps_gpio
> PARAMETER INSTANCE = gpio_ds3231
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_GPIO_WIDTH = 4
> PARAMETER C_BASEADDR = 0x81400000
> PARAMETER C_HIGHADDR = 0x8140ffff
> BUS_INTERFACE SPLB = mb_plb
> PORT GPIO_IO = gpio_ds3231_GPIO_IO
> END
> 
> BEGIN xps_gpio
> PARAMETER INSTANCE = gpio_OW
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_GPIO_WIDTH = 1
> PARAMETER C_BASEADDR = 0x81440000
> PARAMETER C_HIGHADDR = 0x8144ffff
> BUS_INTERFACE SPLB = mb_plb
> PORT GPIO_IO = gpio_OW_GPIO_IO
> END
> 
> BEGIN xps_timer
> PARAMETER INSTANCE = xps_timer_0
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_BASEADDR = 0x83c00000
> PARAMETER C_HIGHADDR = 0x83c0ffff
> BUS_INTERFACE SPLB = mb_plb
> PORT Interrupt = xps_timer_0_Interrupt
> END
> 
> 
> 
> 
> ----- Original Message ----- From: "Vasanth Asokan"
> <vasanth.asokan@xxxxxxxxxx>
> To: <microblaze-uclinux@xxxxxxxxxxxxxx>
> Sent: Monday, July 07, 2008 4:40 PM
> Subject: RE: [microblaze-uclinux] Petalinux with EDK 10.1
> 
> 
>>
>>> -----Original Message-----
>>> From: owner-microblaze-uclinux@xxxxxxxxxxxxxx
>> [mailto:owner-microblaze-
>>> uclinux@xxxxxxxxxxxxxx] On Behalf Of Royce Liao
>>> Sent: Saturday, July 05, 2008 10:31 PM
>>> To: microblaze-uclinux@xxxxxxxxxxxxxx
>>> Subject: RE: [microblaze-uclinux] Petalinux with EDK 10.1
>>>
>>>
>>> > Date: Tue, 17 Jun 2008 09:54:00 +1000
>>> > From: jwilliams@xxxxxxxxxxxxxx
>>> > To: microblaze-uclinux@xxxxxxxxxxxxxx
>>> > Subject: Re: [microblaze-uclinux] Petalinux with EDK 10.1
>>> >
>>> > Sebastian wrote:
>>> >> is it possible to use Xilinx ISE/EDK 10.1 eval with the current
>>> >> petalinux-release (0.30rc1).
>>> >> I'm using a 1600 Spartan3E dev kit.
>>> >
>>> > Yes it is, however the reference designs in
>> hardware/reference-designs
>>> > have are still targetting 9.2.  The S3E1600 reference design should
>>> > rev-up quite nicely if you just copy it and open in XPS.
>> Alternatively,
>>> > you could use Base System Builder to create a new design for the
>> board,
>>> > and do a custom bringup guided by the doco at
>> developer.petalogix.com:
>>> >
>>> > http://developer.petalogix.com/wiki/BoardGuides/Custom/Tutorial
>>>
>>> I've found two minor issues in EDK 10.1 (SP2):
>>>
>>> 1) the Microblaze "CPU_driver (1.11b)" in Webpack 10.1.02 + EDK
>> 10.1.02
>>> removed some #defines needed by Petalinux's  auto-config system.
>>>
>>> In the EDK 10.1.SP2 (XPS) gui, "Software"-> "Software Platform
>> Settings"
>>> Under the tab "Software platform", I can't find the entry for
>>> CORE_CLOCK_FREQ_HZ.. It is no longer there!  When I generate the
>>> libraries, the following files are damaged:
>>>   a)  microblaze_0/include/auto-config.h file contains a broken
>> #define:
>>>        #define CONFIG_XILINX_CPU_CLOCK_FREQ ()  // should contain a #
>>>
>>>   b)microblaze_0/libsrc/petalinux_v1_00_b/Kconfig.auto
>>>     config XILINX_CPU_CLOCK_FREQ
>>>        default    <-- should contain a #!
>>>
>>>   c)microblaze_0/libsrc/petalinux_v1_00_b/auto-config.in
>>>        define_int CONFIG_XILINX_CPU_CLOCK_FREQ <-- should contain a #
>>>
>>
>> The parameter has not been removed, but deprecated. Deprecated
>> parameters do not show up in the GUI.
>>
>> The missing #define value is due to a bug in EDK, where TCL queries for
>> the value of a deprecated parameter are turning up empty. The bug will
>> be fixed in SP3. An answer record (31278) will be available for this
>> issue by tomorrow.
>>
>> The workaround is to explicitly instantiate the parameter in the
>> processor block of the MSS file and give it the right value frequency
>> value.
>>
>> BEGIN PROCESSOR
>> ...
>> PARAMETER CORE_CLOCK_FREQ_HZ = 100000000
>> ...
>> END
>>
>> Also, note that the reason for deprecating the parameter is that the
>> clock frequency information is now directly accessible from the hardware
>> database by reading attributes (if defined in the MHS) off the clock
>> port. Please see the cpu_v1_11_b driver TCL for an example of how to
>> retrieve this value when it is available.
>>
>> Vasanth
>>
>> This email and any attachments are intended for the sole use of the
>> named recipient(s) and contain(s) confidential information that may be
>> proprietary, privileged or copyrighted under applicable law. If you
>> are not the intended recipient, do not read, copy, or forward this
>> email message or any attachments. Delete this email message and any
>> attachments immediately.
>>
>>
>>
>> ___________________________
>> microblaze-uclinux mailing list
>> microblaze-uclinux@xxxxxxxxxxxxxx
>> Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
>> Mailing List Archive :
>> http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
>>
> 
> ___________________________
> microblaze-uclinux mailing list
> microblaze-uclinux@xxxxxxxxxxxxxx
> Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
> Mailing List Archive :
> http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
> 
> 
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- Re: [microblaze-uclinux] Petalinux with EDK 10.1
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