Hello Alex, you need to include the autoconf header (available after using petalinux-copy-autoconfig and a successful kernel built): #include <linux/autoconf.h> all you hardware relevant settings are defined there. Snipsets of the mhs and mss files: . . PORT xps_spi_0_SCK_O_pin = xps_spi_0_SCK_O, DIR = O PORT xps_spi_0_SS_O_pin = xps_spi_0_SS_O, DIR = O, VEC = [0:0] PORT xps_spi_0_MOSI_O_pin = xps_spi_0_MOSI_O, DIR = O PORT xps_spi_0_MISO_I_pin = xps_spi_0_MISO_I, DIR = I . . BEGIN xps_spi PARAMETER INSTANCE = xps_spi_0 PARAMETER HW_VER = 2.00.b PARAMETER C_BASEADDR = 0x84000000 PARAMETER C_HIGHADDR = 0x8400FFFF PARAMETER C_SCK_RATIO = 64 BUS_INTERFACE SPLB = mb_plb PORT SCK_O = xps_spi_0_SCK_O PORT SS_O = xps_spi_0_SS_O PORT MOSI_O = xps_spi_0_MOSI_O PORT MISO_I = xps_spi_0_MISO_I END mss: BEGIN DRIVER PARAMETER DRIVER_NAME = spi PARAMETER DRIVER_VER = 1.11.a PARAMETER HW_INSTANCE = xps_spi_0 END Regards, Marco -----Original Message----- From: owner-microblaze-uclinux@xxxxxxxxxxxxxx on behalf of Alex D. Sent: Tue 11/18/2008 7:49 AM To: microblaze-uclinux@xxxxxxxxxxxxxx Subject: Re: [microblaze-uclinux] Implementing SPI Hi Marco, I used your code. I got errors on the first line, so I used #define CONFIG_XILINX_SPI_0_BASEADDR 0x42000000 to hard code it, since I set my SPI to start at 0x42000000 in my hardware profile (EDK). Unfortunately, I couldn't get it to spit anything out. I'm using arbitraty pins now, and am simply trying to see on an oscilloscope if i can at least drive the pins correctly. It's not working so far. Also, I'm actually using the OPB spi (1.00.e) so the built in driver should work. Again, though, petalinux says it cant find the hardware during start up. When I build the hardware I setup the IRQ, memory address, and pin assignments. I just can't get it to detect. I'd appreciate any help regarding either approach (hardcoded or built in char driver) -Alex On Mon, Nov 3, 2008 at 6:38 AM, Hoefle Marco <Marco.Hoefle@xxxxxxxxxxxxx>wrote: > Hi Alex, > I tried to include the SPI driver as well but had also problems. > Therefore I included a low level header file (from the microblaze libsrc > folder) and used it > in my application directly. It it is a dirty way and not good design > practice as a user space application > should not write to hardware addresses directly but it was for me the > fastest way (I needed it for a demo purpose). > The low level header file (xspi_l.h) contains macros which allow transfers > with only a few lines of code: > > XSpi_mSetControlReg(CONFIG_XILINX_SPI_0_BASEADDR, XSP_CR_ENABLE_MASK | > XSP_CR_MASTER_MODE_MASK | XSP_CR_MANUAL_SS_MASK | XSP_CR_CLK_PHASE_MASK); > XSpi_mSetSlaveSelectReg(CONFIG_XILINX_SPI_0_BASEADDR, 0xFFFFFFFE); > XSpi_mSendByte(CONFIG_XILINX_SPI_0_BASEADDR, val2send); > XSpi_mSendByte(CONFIG_XILINX_SPI_0_BASEADDR, 0xFF); > while( (XSpi_mGetStatusReg(CONFIG_XILINX_SPI_0_BASEADDR) & > XSP_SR_TX_EMPTY_MASK) == 0) > XSpi_mSetSlaveSelectReg(CONFIG_XILINX_SPI_0_BASEADDR, 0xFFFFFFFF); > > I think the driver in petalinux is for a old IP cores on the OPB bus and > might not work with the 2.00.a or 2.00.b SPI cores on the PLB bus (but I am > not sure). > > What might be good for you (from my experience) is to use a chipscope ila > and monitor the SCK, MISO, MOSI and CS signals. > This allows to scope the SPI transfer and debug the application. > Regards, > Marco > > > > > -----Original Message----- > From: owner-microblaze-uclinux@xxxxxxxxxxxxxx on behalf of Alex D. > Sent: Sun 11/2/2008 10:07 AM > To: microblaze-uclinux@xxxxxxxxxxxxxx > Subject: [microblaze-uclinux] Implementing SPI > > Hello all, > > I am a student currently tasked with implementing an SPI to eventually talk > with a DAC and possibly other hardware. I'm using a spartan-3e500-revD > board and have managed to install petalinux into flash and have it boot up > properly. I've also tested a few user apps that interface with the DIP > switches and LED's via the GPIO char driver. > > During the kernel setup I noticed that there is also a char driver for the > SPI, similar to the GPIO drivers I presume. When I go into EDK and ad an > SPI IP core to the reference design I get a a few errors however. They > crop > up during the "Generate Bitstream" process. I keep gettings errors with > the > ucf file voltage levels for the pins (MOSI,SS,SCK) as well as "PAD sharing" > with the flash. I've read that some of the pins for the SPI are shared > with > other devices including the flash. Also, when I simply leave out the MISO > pin, sometimes EDK builds the hardware correctly. However when I boot into > uclinux I get the following error in the log: > > xilinx_spi #0: IO resource(s) not found > xilinx_spi: probe of xilinx_spi.0 failed with error -14 > > > I have a few questions: > > Is it possible to use the SPI IP core and Flash at the same time? > If so how do I go about building the hardware? > > I basically need to get an SPI set up. If i'm going about it the wrong way > I'd appreciate any advice. > > -alex > > > >
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