RE: [microblaze-uclinux] Fwd: SREC File Upload Issues

["William McGinley" <emounty@xxxxxxxxx>]

Hello,

May I add my guess?

>'ddr_sdram_32mx16_wrapper_async_fifo_v4_0_1' is not supported in target
>    'spartan3e'.

It sounds like the device uses the multiport memory controller(mpmc) and
perhaps it was not reconfigured when porting to the Spartan3E ?
I tried to generate a fifo for spartan3e using coregen and I noticed that
the "ECC enable" box is grayed out(?) 

>a missing edif or ngc file,

For this verify that the mpmc_0_wrapper.ngc is in the
\implementation\mpmc_0_wrapper directory


Barry

-----Original Message-----
From: owner-microblaze-uclinux@xxxxxxxxxxxxxx
[mailto:owner-microblaze-uclinux@xxxxxxxxxxxxxx] On Behalf Of Michal Simek
Sent: Wednesday, February 04, 2009 2:42 AM
To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: Re: [microblaze-uclinux] Fwd: SREC File Upload Issues

Hi Matt,

I really don't know but I know that this is right question to Xilinx guys.

> Here are the 3 errors I get again during NGDBUILD:
> 
> ERROR:NgdBuild:604 - logical block
>   
>
'ddr_sdram_32mx16/ddr_sdram_32mx16/DDR_CTRL_I/WO_ECC.RDDATA_PATH_I/V2_ASYNCH
_
>    FIFO_I' with type 'ddr_sdram_32mx16_wrapper_async_fifo_v4_0_1' could
> not be
>    resolved. A pin name misspelling can cause this, a missing edif or
> ngc file,
>    or the misspelling of a type name. Symbol
>    'ddr_sdram_32mx16_wrapper_async_fifo_v4_0_1' is not supported in target
>    'spartan3e'.
> ERROR:NgdBuild:604 - logical block

Here is that problem. You can compare windows and linux mpd files and see
differences.

Regards,
Michal

>
'ddr_sdram_32mx16/ddr_sdram_32mx16/DDR_CTRL_I/WO_ECC.WO_ECC_ASYNC.WRITE_ASYN
C
>    _FIFO_I/V2_ASYNCH_FIFO_DATA' with type
>    'ddr_sdram_32mx16_wrapper_async_fifo_v4_0_3' could not be resolved. A
pin
>    name misspelling can cause this, a missing edif or ngc file, or the
>    misspelling of a type name. Symbol
>    'ddr_sdram_32mx16_wrapper_async_fifo_v4_0_3' is not supported in target
>    'spartan3e'.
> ERROR:NgdBuild:604 - logical block
>   
>
'ddr_sdram_32mx16/ddr_sdram_32mx16/DDR_CTRL_I/WO_ECC.WO_ECC_ASYNC.WRITE_ASYN
C
>    _FIFO_I/V2_ASYNCH_FIFO_CMD' with type
>    'ddr_sdram_32mx16_wrapper_async_fifo_v4_0_2' could not be resolved. A
pin
>    name misspelling can cause this, a missing edif or ngc file, or the
>    misspelling of a type name. Symbol
> 
> Matt
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