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Re: [microblaze-uclinux] uClinux hanging on startup
Hi Stephen
> Hi, I'm using a Spartan3E dev kit to run petalinux/uClinux. Everything was working fine until I added an SPI interface (which I intend to use to communicate with the onboard ADC). Now whenever the OS boots, it freezes at the same particular spot every time. A log of the boot is shown below:
>
> =================================================
> FS-BOOT First Stage Bootloader (c) 2006 PetaLogix
> =================================================
> FS-BOOT: System initialisation completed.
> FS-BOOT: Booting from FLASH. Press 's' for image download.
> FS-BOOT: Booting image...
> SDRAM :
> Enabling caches :
> Icache:OK
> Dcache:OK
> U-Boot Start:0x8ffc0000
> Malloc Start:0x8ff60000
> Board Info Start:0x8ff5ffd0
> Boot Parameters Start:0x8ff4ffd0
> FLASH: 16 MB
> ETHERNET: MAC:00:0a:35:00:22:01
> Hit any key to stop autoboot: 0
> ## Booting image at 890c0000 ...
> Image Name: PetaLinux Kernel 2.6
> Image Type: Microblaze Linux Kernel Image (uncompressed)
> Data Size: 4452387 Bytes = 4.2 MB
> Load Address: 8c000000
> Entry Point: 8c000000
> Verifying Checksum ... OK
> OK
> Linux version 2.6.20-uc0 (stevek@stevek-desktop) (gcc version 3.4.1 ( PetaLinux 0.20 Build -rc1 050607 )) #6 Sun Feb 15 02:06:38 GMT 2009
> setup_cpuinfo: initialising
> setup_cpuinfo: No PVR support in CPU. Using static compile-time info
> set_cpuinfo_static: Using static CPU info.
> setup_memory: max_mapnr: 0x8ffff
> setup_memory: min_low_pfn: 0x8c000
> setup_memory: max_low_pfn: 0x4000
> On node 0 totalpages: 16384
> DMA zone: 128 pages used for memmap
> DMA zone: 0 pages reserved
> DMA zone: 16256 pages, LIFO batch:3
> Normal zone: 0 pages used for memmap
> Built 1 zonelists. Total pages: 16256
> Kernel command line: mtdparts=physmap-flash.0:256K(boot),256K(bootenv),256K(config),5M(image),10M(spare) macaddr=00:0a:35:00:22:01
> OPB INTC #0 at 0x81800000
> PID hash table entries: 256 (order: 8, 1024 bytes)
> Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
> Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
> Memory: 60468k/65536k available
you have doubled size memory -> Set memory size manualy in BSP. On s3e500 is
only 32MB not 64MB, but please keep HW design without any memory change.
Regards,
Michal
> Calibrating delay loop... 24.57 BogoMIPS (lpj=122880)
> Mount-cache hash table entries: 512
> NET: Registered protocol family 16
> NET: Registered protocol family 2
> IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
> TCP established hash table entries: 2048 (order: 1, 8192 bytes)
> TCP bind hash table entries: 1024 (order: 0, 4096 bytes)
> TCP: Hash tables configured (established 2048 bind 1024)
> TCP reno registered
> io scheduler noop registered
> io scheduler anticipatory registered
> io scheduler deadline registered
> io scheduler cfq registered (default)
> xilinx_spi 0: at 0x40A00000 mapped to 0x40A00000, irq=1
> xgpio0 #0 at 0x81400000 mapped to 0x81400000 device: 10,185 not using IRQ
> uartlite.0: ttyS0 at MMIO 0x84000000 (irq = 3) is a uartlite
> RAMDISK driver initialized: 16 RAM disks of 8192K size 1024 blocksize
> eth0: using fifo mode.
> eth0: No PHY detected. Assuming a PHY at address 0.
> eth0: Xilinx EMACLite #0 at 0x81000000 mapped to 0x81000000, irq=2
> physmap platform flash device: 01000000 at 89000000
> physmap-flash.0: Found 1 x16 devices at 0x0 in 8-bit bank
> Intel/Sharp Extended Query Table at 0x0031
> Using buffer write method
> cfi_cmdset_0001: Erase suspend on write enabled
> erase region 0: offset=0x0,size=0x20000,blocks=128
> 5 cmdlinepart partitions found on MTD device physmap-flash.0
> Creating 5 MTD partitions on "physmap-flash.0":
> 0x00000000-0x00040000 : "boot"
> 0x00040000-0x00080000 : "bootenv"
> 0x00080000-0x000c0000 : "config"
> 0x000c0000-0x005c0000 : "image"
> 0x005c0000-0x00fc0000 : "spare"
> uclinux[mtd]: RAM probe address=0x8c220990 size=0x235000
> Creating 1 MTD partitions on "RAM":
> 0x00000000-0x00235000 : "ROMfs"
> uclinux[mtd]: set ROMfs to be root filesystem index=5
> i8042.c: i8042 controller self test timeout.
> TCP cubic registered
> NET: Registered protocol family 1
> VFS: Mounted root (cramfs filesystem) readonly.
> Freeing unused kernel memory: 88k freed
> Mounting proc:
> Mounting var:
> Populating /var:
> Running local start sc
> S
> ---------------------------------------------------------------------------------------
>
> Thats the same output every time I boot. The lack of errors is quite frustrating as I'm unsure what the problem is. If I use the same design minus the SPI core, it boots fine. I'm using the "Xilinx OPB SPI" drivers with an OPB SPI 1.00.e core in EDK. I'm using an OPB to PLB bridge to connect it to everything else. My guess is the SPI is conflicting with the FLASH device as they share a pin but I don't really see how unless I'm missing something. Do I need to modify anything else to get the SPI drivers working? Would bit-banging through a GPIO be an easier route?
>
> ---------------------------------------------------------------------------------------
>
> # ##############################################################################
> # Created by Base System Builder Wizard for Xilinx EDK 10.1.03 Build EDK_K_SP3.6
> # Thu Feb 05 23:20:54 2009
> # Target Board: Xilinx Spartan-3E Starter Board Rev D
> # Family: spartan3e
> # Device: XC3S500e
> # Package: FG320
> # Speed Grade: -4
> # Processor: microblaze_0
> # System clock frequency: 50.00 MHz
> # On Chip Memory : 16 KB
> # Total Off Chip Memory : 80 MB
> # - FLASH = 16 MB
> # - DDR_SDRAM = 64 MB
> # ##############################################################################
> PARAMETER VERSION = 2.1.0
>
> PORT fpga_0_RS232_DCE_RX_pin = fpga_0_RS232_DCE_RX, DIR = I
> PORT fpga_0_RS232_DCE_TX_pin = fpga_0_RS232_DCE_TX, DIR = O
> PORT fpga_0_FLASH_Mem_OEN_pin = fpga_0_FLASH_Mem_OEN, DIR = O
> PORT fpga_0_FLASH_Mem_CEN_pin = fpga_0_FLASH_Mem_CEN, DIR = O, VEC = [0:0]
> PORT fpga_0_FLASH_Mem_WEN_pin = fpga_0_FLASH_Mem_WEN, DIR = O
> PORT fpga_0_FLASH_emc_ben_gnd_pin = net_gnd, DIR = O
> PORT fpga_0_FLASH_Mem_A_pin = fpga_0_FLASH_Mem_A, DIR = O, VEC = [8:31]
> PORT fpga_0_FLASH_Mem_DQ_pin = fpga_0_FLASH_Mem_DQ, DIR = IO, VEC = [0:7]
> PORT fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O = fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O, DIR = IO
> PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk, DIR = O
> PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDRAM_DDR_Clk_n, DIR = O
> PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr, DIR = O, VEC = [12:0]
> PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_DDR_BankAddr, DIR = O, VEC = [1:0]
> PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin = fpga_0_DDR_SDRAM_DDR_CAS_n, DIR = O
> PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE, DIR = O
> PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n, DIR = O
> PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin = fpga_0_DDR_SDRAM_DDR_RAS_n, DIR = O
> PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n, DIR = O
> PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM, DIR = O, VEC = [1:0]
> PORT fpga_0_DDR_SDRAM_DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS, DIR = IO, VEC = [1:0]
> PORT fpga_0_DDR_SDRAM_DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ, DIR = IO, VEC = [15:0]
> PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk, DIR = I
> PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk, DIR = I
> PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs, DIR = I
> PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv, DIR = I
> PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data, DIR = I, VEC = [3:0]
> PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col, DIR = I
> PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er, DIR = I
> PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en, DIR = O
> PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data, DIR = O, VEC = [3:0]
> PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000
> PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RST
> PORT opb_spi_0_SCK_O_pin = opb_spi_0_SCK_O, DIR = O
> PORT opb_spi_0_SS_O_pin = opb_spi_0_SS_O, DIR = O, VEC = [0:0]
>
> BEGIN microblaze
> PARAMETER INSTANCE = microblaze_0
> PARAMETER HW_VER = 7.10.d
> PARAMETER C_USE_ICACHE = 1
> PARAMETER C_CACHE_BYTE_SIZE = 2048
> PARAMETER C_USE_DCACHE = 1
> PARAMETER C_DCACHE_BYTE_SIZE = 2048
> PARAMETER C_DEBUG_ENABLED = 1
> PARAMETER C_ICACHE_BASEADDR = 0x8c000000
> PARAMETER C_ICACHE_HIGHADDR = 0x8fffffff
> PARAMETER C_DCACHE_BASEADDR = 0x8c000000
> PARAMETER C_DCACHE_HIGHADDR = 0x8fffffff
> PARAMETER C_AREA_OPTIMIZED = 1
> PARAMETER C_USE_BARREL = 1
> PARAMETER C_FAMILY = spartan3e
> PARAMETER C_INSTANCE = microblaze_0
> PARAMETER C_FSL_LINKS = 1
> BUS_INTERFACE DPLB = mb_plb
> BUS_INTERFACE IPLB = mb_plb
> BUS_INTERFACE ixcl = ixcl
> BUS_INTERFACE dxcl = dxcl
> BUS_INTERFACE DEBUG = microblaze_0_dbg
> BUS_INTERFACE DLMB = dlmb
> BUS_INTERFACE ILMB = ilmb
> BUS_INTERFACE SFSL0 = fsl_v20_0
> PORT MB_RESET = mb_reset
> PORT Interrupt = Interrupt
> END
> BEGIN plb_v46
> PARAMETER INSTANCE = mb_plb
> PARAMETER HW_VER = 1.03.a
> PORT PLB_Clk = sys_clk_s
> PORT SYS_Rst = sys_bus_reset
> END
> BEGIN lmb_v10
> PARAMETER INSTANCE = ilmb
> PARAMETER HW_VER = 1.00.a
> PORT LMB_Clk = sys_clk_s
> PORT SYS_Rst = sys_bus_reset
> END
> BEGIN lmb_v10
> PARAMETER INSTANCE = dlmb
> PARAMETER HW_VER = 1.00.a
> PORT LMB_Clk = sys_clk_s
> PORT SYS_Rst = sys_bus_reset
> END
> BEGIN lmb_bram_if_cntlr
> PARAMETER INSTANCE = dlmb_cntlr
> PARAMETER HW_VER = 2.10.a
> PARAMETER C_BASEADDR = 0x00000000
> PARAMETER C_HIGHADDR = 0x00001fff
> BUS_INTERFACE SLMB = dlmb
> BUS_INTERFACE BRAM_PORT = dlmb_port
> END
> BEGIN lmb_bram_if_cntlr
> PARAMETER INSTANCE = ilmb_cntlr
> PARAMETER HW_VER = 2.10.a
> PARAMETER C_BASEADDR = 0x00000000
> PARAMETER C_HIGHADDR = 0x00001fff
> BUS_INTERFACE SLMB = ilmb
> BUS_INTERFACE BRAM_PORT = ilmb_port
> END
> BEGIN bram_block
> PARAMETER INSTANCE = lmb_bram
> PARAMETER HW_VER = 1.00.a
> BUS_INTERFACE PORTA = ilmb_port
> BUS_INTERFACE PORTB = dlmb_port
> END
> BEGIN xps_uartlite
> PARAMETER INSTANCE = RS232_DCE
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_BAUDRATE = 115200
> PARAMETER C_DATA_BITS = 8
> PARAMETER C_ODD_PARITY = 0
> PARAMETER C_USE_PARITY = 0
> PARAMETER C_SPLB_CLK_FREQ_HZ = 50000000
> PARAMETER C_BASEADDR = 0x84000000
> PARAMETER C_HIGHADDR = 0x8400ffff
> BUS_INTERFACE SPLB = mb_plb
> PORT RX = fpga_0_RS232_DCE_RX
> PORT TX = fpga_0_RS232_DCE_TX
> PORT Interrupt = RS232_DCE_Interrupt
> END
> BEGIN xps_mch_emc
> PARAMETER INSTANCE = FLASH
> PARAMETER HW_VER = 2.00.a
> PARAMETER C_NUM_CHANNELS = 0
> PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 20000
> PARAMETER C_NUM_BANKS_MEM = 1
> PARAMETER C_MAX_MEM_WIDTH = 8
> PARAMETER C_MEM0_WIDTH = 8
> PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
> PARAMETER C_SYNCH_MEM_0 = 0
> PARAMETER C_TCEDV_PS_MEM_0 = 110000
> PARAMETER C_TWC_PS_MEM_0 = 110000
> PARAMETER C_TAVDV_PS_MEM_0 = 110000
> PARAMETER C_TWP_PS_MEM_0 = 70000
> PARAMETER C_THZCE_PS_MEM_0 = 35000
> PARAMETER C_TLZWE_PS_MEM_0 = 15000
> PARAMETER C_MEM0_BASEADDR = 0x89000000
> PARAMETER C_MEM0_HIGHADDR = 0x89ffffff
> BUS_INTERFACE SPLB = mb_plb
> PORT Mem_A = fpga_0_FLASH_Mem_A_split
> PORT Mem_DQ = fpga_0_FLASH_Mem_DQ
> PORT Mem_OEN = fpga_0_FLASH_Mem_OEN
> PORT Mem_WEN = fpga_0_FLASH_Mem_WEN
> PORT Mem_CEN = fpga_0_FLASH_Mem_CEN
> PORT RdClk = sys_clk_s
> END
> BEGIN mpmc
> PARAMETER INSTANCE = DDR_SDRAM
> PARAMETER HW_VER = 4.03.a
> PARAMETER C_NUM_PORTS = 3
> PARAMETER C_PIM0_BASETYPE = 1
> PARAMETER C_PIM1_BASETYPE = 1
> PARAMETER C_MEM_PARTNO = MT46V32M16-6
> PARAMETER C_SPECIAL_BOARD = S3E_STKIT
> PARAMETER C_MEM_BANKADDR_WIDTH = 2
> PARAMETER C_MEM_DATA_WIDTH = 16
> PARAMETER C_MEM_DQS_WIDTH = 2
> PARAMETER C_MEM_DM_WIDTH = 2
> PARAMETER C_MEM_TYPE = DDR
> PARAMETER C_XCL0_WRITEXFER = 0
> PARAMETER C_PIM2_BASETYPE = 2
> PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000
> PARAMETER C_SPLB2_NATIVE_DWIDTH = 32
> PARAMETER C_MPMC_BASEADDR = 0x8c000000
> PARAMETER C_MPMC_HIGHADDR = 0x8fffffff
> BUS_INTERFACE XCL0 = ixcl
> BUS_INTERFACE XCL1 = dxcl
> BUS_INTERFACE SPLB2 = mb_plb
> PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk
> PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n
> PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr
> PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr
> PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n
> PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE
> PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n
> PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n
> PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n
> PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM
> PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS
> PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ
> PORT DDR_DQS_Div_O = fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O
> PORT DDR_DQS_Div_I = fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O
> PORT MPMC_Clk0 = DDR_SDRAM_mpmc_clk_s
> PORT MPMC_Clk90 = DDR_SDRAM_mpmc_clk_90_s
> PORT MPMC_Rst = sys_periph_reset
> END
> BEGIN xps_ethernetlite
> PARAMETER INSTANCE = Ethernet_MAC
> PARAMETER HW_VER = 2.00.b
> PARAMETER C_SPLB_CLK_PERIOD_PS = 20000
> PARAMETER C_BASEADDR = 0x81000000
> PARAMETER C_HIGHADDR = 0x8100ffff
> BUS_INTERFACE SPLB = mb_plb
> PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk
> PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk
> PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs
> PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv
> PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data
> PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col
> PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er
> PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en
> PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data
> PORT IP2INTC_Irpt = Ethernet_MAC_IP2INTC_Irpt
> END
> BEGIN xps_bram_if_cntlr
> PARAMETER INSTANCE = xps_bram_if_cntlr_1
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_SPLB_NATIVE_DWIDTH = 32
> PARAMETER C_BASEADDR = 0x86a08000
> PARAMETER C_HIGHADDR = 0x86a09fff
> BUS_INTERFACE SPLB = mb_plb
> BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
> END
> BEGIN bram_block
> PARAMETER INSTANCE = xps_bram_if_cntlr_1_bram
> PARAMETER HW_VER = 1.00.a
> BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
> END
> BEGIN xps_timer
> PARAMETER INSTANCE = xps_timer_1
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_COUNT_WIDTH = 32
> PARAMETER C_ONE_TIMER_ONLY = 1
> PARAMETER C_BASEADDR = 0x83c00000
> PARAMETER C_HIGHADDR = 0x83c0ffff
> BUS_INTERFACE SPLB = mb_plb
> PORT Interrupt = xps_timer_1_Interrupt
> END
> BEGIN util_bus_split
> PARAMETER INSTANCE = FLASH_util_bus_split_1
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_SIZE_IN = 32
> PARAMETER C_LEFT_POS = 0
> PARAMETER C_SPLIT = 8
> PORT Sig = fpga_0_FLASH_Mem_A_split
> PORT Out2 = fpga_0_FLASH_Mem_A
> END
> BEGIN clock_generator
> PARAMETER INSTANCE = clock_generator_0
> PARAMETER HW_VER = 2.01.a
> PARAMETER C_EXT_RESET_HIGH = 1
> PARAMETER C_CLKIN_FREQ = 50000000
> PARAMETER C_CLKOUT0_FREQ = 50000000
> PARAMETER C_CLKOUT0_BUF = TRUE
> PARAMETER C_CLKOUT0_PHASE = 0
> PARAMETER C_CLKOUT0_GROUP = NONE
> PARAMETER C_CLKOUT1_FREQ = 100000000
> PARAMETER C_CLKOUT1_BUF = TRUE
> PARAMETER C_CLKOUT1_PHASE = 0
> PARAMETER C_CLKOUT1_GROUP = DCM0
> PARAMETER C_CLKOUT2_FREQ = 100000000
> PARAMETER C_CLKOUT2_BUF = TRUE
> PARAMETER C_CLKOUT2_PHASE = 90
> PARAMETER C_CLKOUT2_GROUP = DCM0
> PORT CLKOUT0 = sys_clk_s
> PORT CLKOUT1 = DDR_SDRAM_mpmc_clk_s
> PORT CLKOUT2 = DDR_SDRAM_mpmc_clk_90_s
> PORT CLKIN = dcm_clk_s
> PORT LOCKED = Dcm_all_locked
> PORT RST = net_gnd
> END
> BEGIN mdm
> PARAMETER INSTANCE = debug_module
> PARAMETER HW_VER = 1.00.d
> PARAMETER C_WRITE_FSL_PORTS = 1
> PARAMETER C_BASEADDR = 0x84400000
> PARAMETER C_HIGHADDR = 0x8440ffff
> BUS_INTERFACE SPLB = mb_plb
> BUS_INTERFACE MBDEBUG_0 = microblaze_0_dbg
> BUS_INTERFACE MFSL0 = fsl_v20_0
> PORT Debug_SYS_Rst = Debug_SYS_Rst
> END
> BEGIN proc_sys_reset
> PARAMETER INSTANCE = proc_sys_reset_0
> PARAMETER HW_VER = 2.00.a
> PARAMETER C_EXT_RESET_HIGH = 1
> PORT Slowest_sync_clk = sys_clk_s
> PORT Dcm_locked = Dcm_all_locked
> PORT Ext_Reset_In = sys_rst_s
> PORT MB_Reset = mb_reset
> PORT Bus_Struct_Reset = sys_bus_reset
> PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
> PORT Peripheral_Reset = sys_periph_reset
> END
> BEGIN xps_intc
> PARAMETER INSTANCE = xps_intc_0
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_BASEADDR = 0x81800000
> PARAMETER C_HIGHADDR = 0x8180ffff
> BUS_INTERFACE SPLB = mb_plb
> PORT Irq = Interrupt
> PORT Intr = RS232_DCE_Interrupt&Ethernet_MAC_IP2INTC_Irpt&opb_spi_0_IP2INTC_Irpt&xps_timer_1_Interrupt
> END
> BEGIN fsl_v20
> PARAMETER INSTANCE = fsl_v20_0
> PARAMETER HW_VER = 2.11.a
> PORT SYS_Rst = sys_rst_s
> PORT FSL_Clk = sys_clk_s
> END
> BEGIN opb_spi
> PARAMETER INSTANCE = opb_spi_0
> PARAMETER HW_VER = 1.00.e
> PARAMETER C_BASEADDR = 0x40a00000
> PARAMETER C_HIGHADDR = 0x40a0ffff
> BUS_INTERFACE SOPB = opb_v20_0
> PORT SCK_O = opb_spi_0_SCK_O
> PORT SPISEL = net_vcc
> PORT SS_O = opb_spi_0_SS_O
> PORT IP2INTC_Irpt = opb_spi_0_IP2INTC_Irpt
> PORT MISO_O = fpga_0_FLASH_Mem_DQ_pin
> END
> BEGIN plbv46_opb_bridge
> PARAMETER INSTANCE = plbv46_opb_bridge_0
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_NUM_ADDR_RNG = 1
> PARAMETER C_RNG0_BASEADDR = 0x40a00000
> PARAMETER C_RNG0_HIGHADDR = 0x40a0ffff
> BUS_INTERFACE SPLB = mb_plb
> BUS_INTERFACE MOPB = opb_v20_0
> END
> BEGIN opb_v20
> PARAMETER INSTANCE = opb_v20_0
> PARAMETER HW_VER = 1.10.c
> PORT OPB_Clk = sys_clk_s
> PORT SYS_Rst = sys_rst_s
> END
> ---------------------------------------------------------------------
> ############################################################################
> ## This system.ucf file is generated by Base System Builder based on the
> ## settings in the selected Xilinx Board Definition file. Please add other
> ## user constraints to this file based on customer design specifications.
> ############################################################################
> Net sys_clk_pin LOC=c9;
> Net sys_clk_pin IOSTANDARD = LVCMOS33;
> Net sys_rst_pin LOC=K17;
> Net sys_rst_pin IOSTANDARD = LVCMOS33;
> Net sys_rst_pin PULLDOWN;
> ## System level constraints
> Net sys_clk_pin TNM_NET = sys_clk_pin;
> TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 20000 ps;
> Net sys_rst_pin TIG;
> ## IO Devices constraints
> #### Module RS232_DCE constraints
> Net fpga_0_RS232_DCE_RX_pin LOC=R7;
> Net fpga_0_RS232_DCE_RX_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_RS232_DCE_TX_pin LOC=M14;
> Net fpga_0_RS232_DCE_TX_pin IOSTANDARD = LVCMOS33;
> #### Module LEDs_8Bit constraints
> #Net fpga_0_LEDs_8Bit_GPIO_d_out_pin LOC=F9;
> #Net fpga_0_LEDs_8Bit_GPIO_d_out_pin IOSTANDARD = LVCMOS33;
> #Net fpga_0_LEDs_8Bit_GPIO_d_out_pin LOC=E9;
> #Net fpga_0_LEDs_8Bit_GPIO_d_out_pin IOSTANDARD = LVCMOS33;
> #Net fpga_0_LEDs_8Bit_GPIO_d_out_pin LOC=D11;
> #Net fpga_0_LEDs_8Bit_GPIO_d_out_pin IOSTANDARD = LVCMOS33;
> #Net fpga_0_LEDs_8Bit_GPIO_d_out_pin LOC=C11;
> #Net fpga_0_LEDs_8Bit_GPIO_d_out_pin IOSTANDARD = LVCMOS33;
> #Net fpga_0_LEDs_8Bit_GPIO_d_out_pin LOC=F11;
> #Net fpga_0_LEDs_8Bit_GPIO_d_out_pin IOSTANDARD = LVCMOS33;
> #Net fpga_0_LEDs_8Bit_GPIO_d_out_pin LOC=E11;
> #Net fpga_0_LEDs_8Bit_GPIO_d_out_pin IOSTANDARD = LVCMOS33;
> #Net fpga_0_LEDs_8Bit_GPIO_d_out_pin LOC=E12;
> #Net fpga_0_LEDs_8Bit_GPIO_d_out_pin IOSTANDARD = LVCMOS33;
> #Net fpga_0_LEDs_8Bit_GPIO_d_out_pin LOC=F12;
> #Net fpga_0_LEDs_8Bit_GPIO_d_out_pin IOSTANDARD = LVCMOS33;
> #### Module FLASH constraints
> Net fpga_0_FLASH_Mem_A_pin LOC=h17;
> Net fpga_0_FLASH_Mem_A_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_A_pin LOC=j13;
> Net fpga_0_FLASH_Mem_A_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_A_pin LOC=j12;
> Net fpga_0_FLASH_Mem_A_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_A_pin LOC=j14;
> Net fpga_0_FLASH_Mem_A_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_A_pin LOC=j15;
> Net fpga_0_FLASH_Mem_A_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_A_pin LOC=j16;
> Net fpga_0_FLASH_Mem_A_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_A_pin LOC=j17;
> Net fpga_0_FLASH_Mem_A_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_A_pin LOC=k14;
> Net fpga_0_FLASH_Mem_A_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_A_pin LOC=k15;
> Net fpga_0_FLASH_Mem_A_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_A_pin LOC=k12;
> Net fpga_0_FLASH_Mem_A_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_A_pin LOC=k13;
> Net fpga_0_FLASH_Mem_A_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_A_pin LOC=l15;
> Net fpga_0_FLASH_Mem_A_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_A_pin LOC=l16;
> Net fpga_0_FLASH_Mem_A_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_A_pin LOC=t18;
> Net fpga_0_FLASH_Mem_A_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_A_pin LOC=r18;
> Net fpga_0_FLASH_Mem_A_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_A_pin LOC=t17;
> Net fpga_0_FLASH_Mem_A_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_A_pin LOC=u18;
> Net fpga_0_FLASH_Mem_A_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_A_pin LOC=t16;
> Net fpga_0_FLASH_Mem_A_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_A_pin LOC=u15;
> Net fpga_0_FLASH_Mem_A_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_A_pin LOC=v15;
> Net fpga_0_FLASH_Mem_A_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_A_pin LOC=t12;
> Net fpga_0_FLASH_Mem_A_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_A_pin LOC=v13;
> Net fpga_0_FLASH_Mem_A_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_A_pin LOC=v12;
> Net fpga_0_FLASH_Mem_A_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_A_pin LOC=n11;
> Net fpga_0_FLASH_Mem_A_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_DQ_pin LOC=n10;
> Net fpga_0_FLASH_Mem_DQ_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_DQ_pin LOC=p10;
> Net fpga_0_FLASH_Mem_DQ_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_DQ_pin LOC=r10;
> Net fpga_0_FLASH_Mem_DQ_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_DQ_pin LOC=v9;
> Net fpga_0_FLASH_Mem_DQ_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_DQ_pin LOC=u9;
> Net fpga_0_FLASH_Mem_DQ_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_DQ_pin LOC=r9;
> Net fpga_0_FLASH_Mem_DQ_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_DQ_pin LOC=m9;
> Net fpga_0_FLASH_Mem_DQ_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_DQ_pin LOC=n9;
> Net fpga_0_FLASH_Mem_DQ_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_OEN_pin LOC=c18;
> Net fpga_0_FLASH_Mem_OEN_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_WEN_pin LOC=d17;
> Net fpga_0_FLASH_Mem_WEN_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_Mem_CEN_pin LOC=d16;
> Net fpga_0_FLASH_Mem_CEN_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_FLASH_emc_ben_gnd_pin LOC=c17;
> Net fpga_0_FLASH_emc_ben_gnd_pin IOSTANDARD = LVCMOS33;
> #### Module DDR_SDRAM constraints
> Net fpga_0_DDR_SDRAM_DDR_Clk_pin LOC=J5;
> Net fpga_0_DDR_SDRAM_DDR_Clk_pin IOSTANDARD = DIFF_SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_Clk_n_pin LOC=J4;
> Net fpga_0_DDR_SDRAM_DDR_Clk_n_pin IOSTANDARD = DIFF_SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_Addr_pin LOC=T1;
> Net fpga_0_DDR_SDRAM_DDR_Addr_pin IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_Addr_pin LOC=R3;
> Net fpga_0_DDR_SDRAM_DDR_Addr_pin IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_Addr_pin LOC=R2;
> Net fpga_0_DDR_SDRAM_DDR_Addr_pin IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_Addr_pin LOC=P1;
> Net fpga_0_DDR_SDRAM_DDR_Addr_pin IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_Addr_pin LOC=F4;
> Net fpga_0_DDR_SDRAM_DDR_Addr_pin IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_Addr_pin LOC=H4;
> Net fpga_0_DDR_SDRAM_DDR_Addr_pin IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_Addr_pin LOC=H3;
> Net fpga_0_DDR_SDRAM_DDR_Addr_pin IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_Addr_pin LOC=H1;
> Net fpga_0_DDR_SDRAM_DDR_Addr_pin IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_Addr_pin LOC=H2;
> Net fpga_0_DDR_SDRAM_DDR_Addr_pin IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_Addr_pin LOC=N4;
> Net fpga_0_DDR_SDRAM_DDR_Addr_pin IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_Addr_pin LOC=T2;
> Net fpga_0_DDR_SDRAM_DDR_Addr_pin IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_Addr_pin LOC=N5;
> Net fpga_0_DDR_SDRAM_DDR_Addr_pin IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_Addr_pin LOC=P2;
> Net fpga_0_DDR_SDRAM_DDR_Addr_pin IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin LOC=K5;
> Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin LOC=K6;
> Net fpga_0_DDR_SDRAM_DDR_BankAddr_pin IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_CAS_n_pin LOC=C2;
> Net fpga_0_DDR_SDRAM_DDR_CAS_n_pin IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_CE_pin LOC=K3;
> Net fpga_0_DDR_SDRAM_DDR_CE_pin IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_CS_n_pin LOC=K4;
> Net fpga_0_DDR_SDRAM_DDR_CS_n_pin IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_RAS_n_pin LOC=C1;
> Net fpga_0_DDR_SDRAM_DDR_RAS_n_pin IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_WE_n_pin LOC=D1;
> Net fpga_0_DDR_SDRAM_DDR_WE_n_pin IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_DM_pin LOC=J2;
> Net fpga_0_DDR_SDRAM_DDR_DM_pin IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_DM_pin LOC=J1;
> Net fpga_0_DDR_SDRAM_DDR_DM_pin IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_DQS LOC=L6;
> Net fpga_0_DDR_SDRAM_DDR_DQS IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_DQS LOC=G3;
> Net fpga_0_DDR_SDRAM_DDR_DQS IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_DQS PULLUP;
> Net fpga_0_DDR_SDRAM_DDR_DQ LOC=L2;
> Net fpga_0_DDR_SDRAM_DDR_DQ IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_DQ PULLUP;
> Net fpga_0_DDR_SDRAM_DDR_DQ LOC=L1;
> Net fpga_0_DDR_SDRAM_DDR_DQ IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_DQ PULLUP;
> Net fpga_0_DDR_SDRAM_DDR_DQ LOC=L3;
> Net fpga_0_DDR_SDRAM_DDR_DQ IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_DQ PULLUP;
> Net fpga_0_DDR_SDRAM_DDR_DQ LOC=L4;
> Net fpga_0_DDR_SDRAM_DDR_DQ IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_DQ PULLUP;
> Net fpga_0_DDR_SDRAM_DDR_DQ LOC=M3;
> Net fpga_0_DDR_SDRAM_DDR_DQ IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_DQ PULLUP;
> Net fpga_0_DDR_SDRAM_DDR_DQ LOC=M4;
> Net fpga_0_DDR_SDRAM_DDR_DQ IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_DQ PULLUP;
> Net fpga_0_DDR_SDRAM_DDR_DQ LOC=M5;
> Net fpga_0_DDR_SDRAM_DDR_DQ IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_DQ PULLUP;
> Net fpga_0_DDR_SDRAM_DDR_DQ LOC=M6;
> Net fpga_0_DDR_SDRAM_DDR_DQ IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_DQ PULLUP;
> Net fpga_0_DDR_SDRAM_DDR_DQ LOC=E2;
> Net fpga_0_DDR_SDRAM_DDR_DQ IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_DQ PULLUP;
> Net fpga_0_DDR_SDRAM_DDR_DQ LOC=E1;
> Net fpga_0_DDR_SDRAM_DDR_DQ IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_DQ PULLUP;
> Net fpga_0_DDR_SDRAM_DDR_DQ LOC=F1;
> Net fpga_0_DDR_SDRAM_DDR_DQ IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_DQ PULLUP;
> Net fpga_0_DDR_SDRAM_DDR_DQ LOC=F2;
> Net fpga_0_DDR_SDRAM_DDR_DQ IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_DQ PULLUP;
> Net fpga_0_DDR_SDRAM_DDR_DQ LOC=G6;
> Net fpga_0_DDR_SDRAM_DDR_DQ IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_DQ PULLUP;
> Net fpga_0_DDR_SDRAM_DDR_DQ LOC=G5;
> Net fpga_0_DDR_SDRAM_DDR_DQ IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_DQ PULLUP;
> Net fpga_0_DDR_SDRAM_DDR_DQ LOC=H6;
> Net fpga_0_DDR_SDRAM_DDR_DQ IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_DQ PULLUP;
> Net fpga_0_DDR_SDRAM_DDR_DQ LOC=H5;
> Net fpga_0_DDR_SDRAM_DDR_DQ IOSTANDARD = SSTL2_I;
> Net fpga_0_DDR_SDRAM_DDR_DQ PULLUP;
> Net fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O LOC=P13;
> Net fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O IOSTANDARD = LVCMOS33;
> Net fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O LOC=P13;
> Net fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O IOSTANDARD = LVCMOS33;
> #### Module Ethernet_MAC constraints
> Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin LOC=T7;
> Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin CLOCK_DEDICATED_ROUTE = FALSE;
> Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin LOC=V3;
> Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin CLOCK_DEDICATED_ROUTE = FALSE;
> Net fpga_0_Ethernet_MAC_PHY_crs_pin LOC=U13;
> Net fpga_0_Ethernet_MAC_PHY_crs_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_Ethernet_MAC_PHY_dv_pin LOC=V2;
> Net fpga_0_Ethernet_MAC_PHY_dv_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_Ethernet_MAC_PHY_rx_data_pin LOC=V8;
> Net fpga_0_Ethernet_MAC_PHY_rx_data_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_Ethernet_MAC_PHY_rx_data_pin LOC=T11;
> Net fpga_0_Ethernet_MAC_PHY_rx_data_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_Ethernet_MAC_PHY_rx_data_pin LOC=U11;
> Net fpga_0_Ethernet_MAC_PHY_rx_data_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_Ethernet_MAC_PHY_rx_data_pin LOC=V14;
> Net fpga_0_Ethernet_MAC_PHY_rx_data_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_Ethernet_MAC_PHY_col_pin LOC=U6;
> Net fpga_0_Ethernet_MAC_PHY_col_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_Ethernet_MAC_PHY_rx_er_pin LOC=U14;
> Net fpga_0_Ethernet_MAC_PHY_rx_er_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_Ethernet_MAC_PHY_tx_en_pin LOC=P15;
> Net fpga_0_Ethernet_MAC_PHY_tx_en_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_Ethernet_MAC_PHY_tx_data_pin LOC=R11;
> Net fpga_0_Ethernet_MAC_PHY_tx_data_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_Ethernet_MAC_PHY_tx_data_pin LOC=T15;
> Net fpga_0_Ethernet_MAC_PHY_tx_data_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_Ethernet_MAC_PHY_tx_data_pin LOC=R5;
> Net fpga_0_Ethernet_MAC_PHY_tx_data_pin IOSTANDARD = LVCMOS33;
> Net fpga_0_Ethernet_MAC_PHY_tx_data_pin LOC=T5;
> Net fpga_0_Ethernet_MAC_PHY_tx_data_pin IOSTANDARD = LVCMOS33;
> # ADC controller
> Net opb_spi_0_SS_O_pin LOC=P11 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
> Net opb_spi_0_SCK_O_pin LOC=U16 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
>
> ---------------------------------------------------------------------
>
> Any help would be greatly appreciated,
> Stephen
> _________________________________________________________________
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>
>
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