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Re: [microblaze-uclinux] troubles with Petalinux and libgen in XPS 11.1
> There is a problem in your Kconfig,.auto file - the IRQ number assignments
> are not there. Causes:
>
> 1 - bad HW design with peripheral IRQs not connected
> 2 - failure to correctly apply the 11.1 patch for the petalinux BSP tools
> 3 - failure to actually rebuild the Kconfig.auto. in your HW project, do
> "make -f system.make libsclean", then rebuild the libs, to be sure. Then,
> do copy-autoconfig.
Yes it was the 1st cause John mention.
And it was simplest to start the design again from start than adding
thoses IRQs.
Now from the Petalinux size it seems ok, eveything compiles but U-boot
displays nothing although fs-boot starts properly.
I have tempted to configure same HW in XPS-11.1 that the one I have
which works from XPS-10.1
I have checked again that UART is properly configured in XPS 11.1
I use the same petalinux configuration that works with my design from 10.1.
Petalinux compiled for 11.1 do not starts but displays at least
messages on HW config from 10.1
I have double check the petalinux-copy-autoconfig from switching from
one design to the other ...
I load the new u-boot.srec.
I may have miss one step or a default option have changed between XPS
versions ...
Any idea ?
I have had this error message in XPS but files where generated successfully:
ERROR:EDK:3234 - request for property: handletype of a MODULE not handled.
Bellow is my XPS console output.
Nicolas
----
Copied /opt/Xilinx/11.1/EDK/data/xflow/bitgen.ut to etc directory
Copied /opt/Xilinx/11.1/EDK/data/xflow/bitgen.ut to etc directory
Generating Block Diagram :
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/blockdiagram/system.svg...
Generating Block Diagram :
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/blockdiagram/system.svg...
Generated --- system.svg
Generated --- system.svg
Generating Block Diagram :
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/blockdiagram/system.svg...
Generating Block Diagram :
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/blockdiagram/system.svg...
Generated --- system.svg
Generated --- system.svg
Saved MSS File.
Saved MSS File.
Saved MSS File.
Saved MSS File.
At Local date and time: Thu Jun 18 21:42:40 2009
make -f system.make bits started...
****************************************************
Creating system netlist for hardware specification..
****************************************************
platgen -p xc4vsx35ff668-10 -lang vhdl -lp
/home/users/nicolas/research/SoPC/OS/petalinux-svn/hardware/edk_user_repository/
-msg __xps/ise/xmsgprops.lst system.mhs
Release Xilinx EDK 11.1 - platgen EDK_L.29.1
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
Command Line: platgen -p xc4vsx35ff668-10 -lang vhdl -lp
/home/users/nicolas/research/SoPC/OS/petalinux-svn/hardware/edk_user_repository/
-msg __xps/ise/xmsgprops.lst system.mhs
Parse system.mhs ...
Read MPD definitions ...
/opt/Xilinx/11.1/EDK /opt/Xilinx/11.1/EDK /opt/Xilinx/11.1/ISE
Overriding IP level properties ...
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 199 - tcl is overriding PARAMETER C_MEM_PART_DATA_WIDTH value
to 16
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 203 - tcl is overriding PARAMETER C_MEM_PART_TRAS value to
45000
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 204 - tcl is overriding PARAMETER C_MEM_PART_TRASMAX value to
120000000
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 205 - tcl is overriding PARAMETER C_MEM_PART_TRC value to 65000
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 206 - tcl is overriding PARAMETER C_MEM_PART_TRCD value to
20000
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 208 - tcl is overriding PARAMETER C_MEM_PART_TWR value to 15000
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 209 - tcl is overriding PARAMETER C_MEM_PART_TRP value to 20000
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 210 - tcl is overriding PARAMETER C_MEM_PART_TMRD value to 2
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 211 - tcl is overriding PARAMETER C_MEM_PART_TRRD value to
15000
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 212 - tcl is overriding PARAMETER C_MEM_PART_TRFC value to
75000
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 213 - tcl is overriding PARAMETER C_MEM_PART_TREFI value to
7800000
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 218 - tcl is overriding PARAMETER C_MEM_PART_CAS_A_FMAX value
to 133
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 219 - tcl is overriding PARAMETER C_MEM_PART_CAS_A value to 2
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 220 - tcl is overriding PARAMETER C_MEM_PART_CAS_B_FMAX value
to 143
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 221 - tcl is overriding PARAMETER C_MEM_PART_CAS_B value to 2.5
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Address Map for Processor microblaze_0
(0000000000-0x00001fff) dlmb_cntlr dlmb
(0000000000-0x00001fff) ilmb_cntlr ilmb
(0x44000000-0x47ffffff) DDR_SDRAM microblaze_0_DXCL
(0x44000000-0x47ffffff) DDR_SDRAM microblaze_0_IXCL
(0x80800000-0x80ffffff) FLASH mb_plb
(0x81000000-0x8100ffff) Ethernet_MAC mb_plb
(0x81800000-0x8180ffff) xps_intc_0 mb_plb
(0x83c00000-0x83c0ffff) xps_timer_0 mb_plb
(0x84000000-0x8400ffff) RS232_Uart mb_plb
(0x84400000-0x8440ffff) mdm_0 mb_plb
Computing clock values...
INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:mb_plb -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/plb_v46_v1_04_a/data/plb_
v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER C_PLBV46_NUM_MASTERS
value to 2
INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:mb_plb -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/plb_v46_v1_04_a/data/plb_
v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_PLBV46_NUM_SLAVES
value to 6
INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:mb_plb -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/plb_v46_v1_04_a/data/plb_
v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_PLBV46_MID_WIDTH
value to 1
INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:mb_plb -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/plb_v46_v1_04_a/data/plb_
v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH value
to 32
INFO:EDK:1560 - IPNAME:lmb_v10 INSTANCE:ilmb -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/data/lmb_
v10_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_LMB_NUM_SLAVES value
to 1
INFO:EDK:1560 - IPNAME:lmb_v10 INSTANCE:dlmb -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/data/lmb_
v10_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_LMB_NUM_SLAVES value
to 1
INFO:EDK:1560 - IPNAME:bram_block INSTANCE:lmb_bram -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/bram_block_v1_00_a/data/b
ram_block_v2_1_0.mpd line 69 - tool is overriding PARAMETER C_MEMSIZE value
to 0x2000
INFO:EDK:1560 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/xps_ethernetlite_v2_01_a/
data/xps_ethernetlite_v2_1_0.mpd line 78 - tool is overriding PARAMETER
C_SPLB_NUM_MASTERS value to 2
INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:FLASH -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_00_a/data/
xps_mch_emc_v2_1_0.mpd line 80 - tool is overriding PARAMETER
C_SPLB_NUM_MASTERS value to 2
INFO:EDK:1560 - IPNAME:xps_uartlite INSTANCE:RS232_Uart -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/xps_uartlite_v1_01_a/data
/xps_uartlite_v2_1_0.mpd line 76 - tool is overriding PARAMETER
C_SPLB_NUM_MASTERS value to 2
INFO:EDK:1560 - IPNAME:xps_timer INSTANCE:xps_timer_0 -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/xps_timer_v1_01_a/data/xp
s_timer_v2_1_0.mpd line 79 - tool is overriding PARAMETER C_SPLB_MID_WIDTH
value to 1
INFO:EDK:1560 - IPNAME:xps_timer INSTANCE:xps_timer_0 -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/xps_timer_v1_01_a/data/xp
s_timer_v2_1_0.mpd line 80 - tool is overriding PARAMETER C_SPLB_NUM_MASTERS
value to 2
INFO:EDK:1560 - IPNAME:mdm INSTANCE:mdm_0 -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_e/data/mdm_v2_1
_0.mpd line 88 - tool is overriding PARAMETER C_SPLB_MID_WIDTH value to 1
INFO:EDK:1560 - IPNAME:mdm INSTANCE:mdm_0 -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_e/data/mdm_v2_1
_0.mpd line 89 - tool is overriding PARAMETER C_SPLB_NUM_MASTERS value to 2
INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/xps_intc_v2_00_a/data/xps
_intc_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_SPLB_NUM_MASTERS
value to 2
Checking platform address map ...
Checking platform configuration ...
INFO:EDK:1563 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mhs line 163
- This design requires design constraints to guarantee performance.
Please refer to the xps_ethernetlite_v2_00_a data sheet for details.
The PLB clock frequency must be greater than or equal to 50 MHz for 100 Mbs
Ethernet operation and greater than or equal to 5.0 MHz for 10 Mbs Ethernet
operation.
IPNAME:plb_v46 INSTANCE:mb_plb -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mhs line 79 - 2
master(s) : 6 slave(s)
IPNAME:lmb_v10 INSTANCE:ilmb -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mhs line 87 - 1
master(s) : 1 slave(s)
IPNAME:lmb_v10 INSTANCE:dlmb -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mhs line 94 - 1
master(s) : 1 slave(s)
Checking port drivers...
WARNING:EDK:2098 - PORT:IWAIT CONNECTOR:ilmb_LMB_Wait -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_20_a/data/m
icroblaze_v2_1_0.mpd line 234 - No driver found. Port will be driven to GND!
WARNING:EDK:2098 - PORT:DWAIT CONNECTOR:dlmb_LMB_Wait -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_20_a/data/m
icroblaze_v2_1_0.mpd line 270 - No driver found. Port will be driven to GND!
WARNING:EDK:2098 - PORT:bscan_tdo1 CONNECTOR:bscan_tdo1 -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_e/data/mdm_v2_1
_0.mpd line 230 - No driver found. Port will be driven to GND!
WARNING:EDK:2099 - PORT:I_ADDRTAG CONNECTOR:ilmb_M_ADDRTAG -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_20_a/data/m
icroblaze_v2_1_0.mpd line 232 - floating connection!
WARNING:EDK:2099 - PORT:D_ADDRTAG CONNECTOR:dlmb_M_ADDRTAG -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_20_a/data/m
icroblaze_v2_1_0.mpd line 273 - floating connection!
WARNING:EDK:2099 - PORT:bscan_tdi CONNECTOR:bscan_tdi -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_e/data/mdm_v2_1
_0.mpd line 223 - floating connection!
WARNING:EDK:2099 - PORT:bscan_reset CONNECTOR:bscan_reset -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_e/data/mdm_v2_1
_0.mpd line 224 - floating connection!
WARNING:EDK:2099 - PORT:bscan_shift CONNECTOR:bscan_shift -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_e/data/mdm_v2_1
_0.mpd line 225 - floating connection!
WARNING:EDK:2099 - PORT:bscan_update CONNECTOR:bscan_update -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_e/data/mdm_v2_1
_0.mpd line 226 - floating connection!
WARNING:EDK:2099 - PORT:bscan_capture CONNECTOR:bscan_capture -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_e/data/mdm_v2_1
_0.mpd line 227 - floating connection!
WARNING:EDK:2099 - PORT:bscan_sel1 CONNECTOR:bscan_sel1 -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_e/data/mdm_v2_1
_0.mpd line 228 - floating connection!
WARNING:EDK:2099 - PORT:bscan_drck1 CONNECTOR:bscan_drck1 -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_e/data/mdm_v2_1
_0.mpd line 229 - floating connection!
Performing Clock DRCs...
Performing Reset DRCs...
Overriding system level properties...
INFO:EDK:1560 - IPNAME:microblaze INSTANCE:microblaze_0 -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_20_a/data/m
icroblaze_v2_1_0.mpd line 157 - tcl is overriding PARAMETER C_D_PLB value to
1
INFO:EDK:1560 - IPNAME:microblaze INSTANCE:microblaze_0 -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_20_a/data/m
icroblaze_v2_1_0.mpd line 158 - tcl is overriding PARAMETER C_D_OPB value to
0
INFO:EDK:1560 - IPNAME:microblaze INSTANCE:microblaze_0 -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_20_a/data/m
icroblaze_v2_1_0.mpd line 160 - tcl is overriding PARAMETER C_I_PLB value to
1
INFO:EDK:1560 - IPNAME:microblaze INSTANCE:microblaze_0 -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_20_a/data/m
icroblaze_v2_1_0.mpd line 161 - tcl is overriding PARAMETER C_I_OPB value to
0
INFO:EDK:1560 - IPNAME:microblaze INSTANCE:microblaze_0 -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_20_a/data/m
icroblaze_v2_1_0.mpd line 196 - tcl is overriding PARAMETER C_ADDR_TAG_BITS
value to 13
INFO:EDK:1560 - IPNAME:microblaze INSTANCE:microblaze_0 -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_20_a/data/m
icroblaze_v2_1_0.mpd line 206 - tcl is overriding PARAMETER C_DCACHE_ADDR_TAG
value to 13
INFO:EDK:1560 - IPNAME:microblaze INSTANCE:microblaze_0 -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_20_a/data/m
icroblaze_v2_1_0.mpd line 218 - tcl is overriding PARAMETER C_USE_INTERRUPT
value to 1
INFO:EDK:1560 - IPNAME:microblaze INSTANCE:microblaze_0 -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_20_a/data/m
icroblaze_v2_1_0.mpd line 219 - tcl is overriding PARAMETER C_USE_EXT_BRK
value to 1
INFO:EDK:1560 - IPNAME:microblaze INSTANCE:microblaze_0 -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_20_a/data/m
icroblaze_v2_1_0.mpd line 220 - tcl is overriding PARAMETER C_USE_EXT_NM_BRK
value to 1
INFO:EDK:1560 - IPNAME:lmb_bram_if_cntlr INSTANCE:dlmb_cntlr -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v2_10_b
/data/lmb_bram_if_cntlr_v2_1_0.mpd line 77 - tcl is overriding PARAMETER
C_MASK value to 0x84000000
INFO:EDK:1560 - IPNAME:lmb_bram_if_cntlr INSTANCE:ilmb_cntlr -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v2_10_b
/data/lmb_bram_if_cntlr_v2_1_0.mpd line 77 - tcl is overriding PARAMETER
C_MASK value to 0x84000000
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 227 - tcl is overriding PARAMETER C_MEM_CAS_LATENCY value to 2
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 261 - tcl is overriding PARAMETER C_PIM0_SUBTYPE value to IXCL
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 312 - tcl is overriding PARAMETER C_PIM1_SUBTYPE value to DXCL
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 664 - tcl is overriding PARAMETER C_WR_TRAINING_PORT value to 1
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 679 - tcl is overriding PARAMETER
C_CTRL_DP_RDFIFO_WHICHPORT_DELAY value to 0xb
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 682 - tcl is overriding PARAMETER
C_CTRL_PHYIF_DUMMYREADSTART_DELAY value to 0x5
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 689 - tcl is overriding PARAMETER C_CTRL_Q6_DELAY value to 0x4
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 690 - tcl is overriding PARAMETER C_CTRL_Q7_DELAY value to 0x0
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 691 - tcl is overriding PARAMETER C_CTRL_Q8_DELAY value to 0x0
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 692 - tcl is overriding PARAMETER C_CTRL_Q9_DELAY value to 0x0
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 694 - tcl is overriding PARAMETER C_CTRL_Q11_DELAY value to 0x0
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 695 - tcl is overriding PARAMETER C_CTRL_Q12_DELAY value to 0x1
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 696 - tcl is overriding PARAMETER C_CTRL_Q13_DELAY value to 0x1
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 700 - tcl is overriding PARAMETER C_CTRL_Q17_DELAY value to 0x0
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 701 - tcl is overriding PARAMETER C_CTRL_Q18_DELAY value to 0x0
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 702 - tcl is overriding PARAMETER C_CTRL_Q19_DELAY value to 0x0
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 703 - tcl is overriding PARAMETER C_CTRL_Q20_DELAY value to 0x0
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 704 - tcl is overriding PARAMETER C_CTRL_Q21_DELAY value to 0x0
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 705 - tcl is overriding PARAMETER C_CTRL_Q22_DELAY value to 0x0
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 706 - tcl is overriding PARAMETER C_CTRL_Q23_DELAY value to 0x0
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 707 - tcl is overriding PARAMETER C_CTRL_Q24_DELAY value to 0x0
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 708 - tcl is overriding PARAMETER C_CTRL_Q25_DELAY value to 0x0
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 709 - tcl is overriding PARAMETER C_CTRL_Q26_DELAY value to 0x0
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 710 - tcl is overriding PARAMETER C_CTRL_Q27_DELAY value to 0x0
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 711 - tcl is overriding PARAMETER C_CTRL_Q28_DELAY value to 0x0
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 712 - tcl is overriding PARAMETER C_CTRL_Q29_DELAY value to 0x0
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 713 - tcl is overriding PARAMETER C_CTRL_Q30_DELAY value to 0x0
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 714 - tcl is overriding PARAMETER C_CTRL_Q31_DELAY value to 0x0
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 715 - tcl is overriding PARAMETER C_CTRL_Q32_DELAY value to 0x1
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 716 - tcl is overriding PARAMETER C_CTRL_Q33_DELAY value to 0x1
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 717 - tcl is overriding PARAMETER C_CTRL_Q34_DELAY value to 0x0
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 718 - tcl is overriding PARAMETER C_CTRL_Q35_DELAY value to 0x0
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 719 - tcl is overriding PARAMETER C_SKIP_1_VALUE value to 0x001
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 720 - tcl is overriding PARAMETER C_SKIP_2_VALUE value to 0x001
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 721 - tcl is overriding PARAMETER C_SKIP_3_VALUE value to 0x001
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 722 - tcl is overriding PARAMETER C_SKIP_4_VALUE value to 0x001
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 723 - tcl is overriding PARAMETER C_SKIP_5_VALUE value to 0x001
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 724 - tcl is overriding PARAMETER C_SKIP_6_VALUE value to 0x001
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 725 - tcl is overriding PARAMETER C_SKIP_7_VALUE value to 0x001
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 727 - tcl is overriding PARAMETER C_B32_REPEAT_CNT value to 2
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 728 - tcl is overriding PARAMETER C_B64_REPEAT_CNT value to 6
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 730 - tcl is overriding PARAMETER C_HIGHADDR_CTRL0 value to
0x008
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 731 - tcl is overriding PARAMETER C_BASEADDR_CTRL1 value to
0x009
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 732 - tcl is overriding PARAMETER C_HIGHADDR_CTRL1 value to
0x00f
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 733 - tcl is overriding PARAMETER C_BASEADDR_CTRL2 value to
0x010
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 734 - tcl is overriding PARAMETER C_HIGHADDR_CTRL2 value to
0x018
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 735 - tcl is overriding PARAMETER C_BASEADDR_CTRL3 value to
0x019
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 736 - tcl is overriding PARAMETER C_HIGHADDR_CTRL3 value to
0x01f
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 737 - tcl is overriding PARAMETER C_BASEADDR_CTRL4 value to
0x020
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 738 - tcl is overriding PARAMETER C_HIGHADDR_CTRL4 value to
0x029
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 739 - tcl is overriding PARAMETER C_BASEADDR_CTRL5 value to
0x02a
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 740 - tcl is overriding PARAMETER C_HIGHADDR_CTRL5 value to
0x030
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 741 - tcl is overriding PARAMETER C_BASEADDR_CTRL6 value to
0x031
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 742 - tcl is overriding PARAMETER C_HIGHADDR_CTRL6 value to
0x03c
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 743 - tcl is overriding PARAMETER C_BASEADDR_CTRL7 value to
0x03d
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 744 - tcl is overriding PARAMETER C_HIGHADDR_CTRL7 value to
0x044
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 745 - tcl is overriding PARAMETER C_BASEADDR_CTRL8 value to
0x045
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 746 - tcl is overriding PARAMETER C_HIGHADDR_CTRL8 value to
0x054
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 747 - tcl is overriding PARAMETER C_BASEADDR_CTRL9 value to
0x055
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 748 - tcl is overriding PARAMETER C_HIGHADDR_CTRL9 value to
0x060
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 749 - tcl is overriding PARAMETER C_BASEADDR_CTRL10 value to
0x061
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 750 - tcl is overriding PARAMETER C_HIGHADDR_CTRL10 value to
0x070
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 751 - tcl is overriding PARAMETER C_BASEADDR_CTRL11 value to
0x071
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 752 - tcl is overriding PARAMETER C_HIGHADDR_CTRL11 value to
0x07c
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 753 - tcl is overriding PARAMETER C_BASEADDR_CTRL12 value to
0x07d
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 754 - tcl is overriding PARAMETER C_HIGHADDR_CTRL12 value to
0x08c
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 755 - tcl is overriding PARAMETER C_BASEADDR_CTRL13 value to
0x08d
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 756 - tcl is overriding PARAMETER C_HIGHADDR_CTRL13 value to
0x098
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 757 - tcl is overriding PARAMETER C_BASEADDR_CTRL14 value to
0x099
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 758 - tcl is overriding PARAMETER C_HIGHADDR_CTRL14 value to
0x0a2
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 759 - tcl is overriding PARAMETER C_BASEADDR_CTRL15 value to
0x0a3
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 760 - tcl is overriding PARAMETER C_HIGHADDR_CTRL15 value to
0x0a4
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 799 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_19 value to
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 800 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_18 value to
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 801 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_17 value to
0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 804 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_14 value to
0x000002FC000002FC000002FC0000003C0000003C0000003C0000003C0000003C
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 805 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_13 value to
0x0000003C0000003C0000003D0000003C000000300000003C000040280000003C
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 806 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_12 value to
0x000040280000003C000004340000243C000004350000243C000004340000243C
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 807 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_11 value to
0x000004340000943C000080380001003C0001003C000140280001003C0001003C
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 808 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_10 value to
0x0001003D0001003C000101240001213C000101240001213C000101240001213C
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 809 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_0F value to
0x000101240001913C000180380000003C000040280000003C000004340000243C
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 810 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_0E value to
0x000004350000243C000004340000243C000004340000943C000080380001003C
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 811 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_0D value to
0x0001003C000140280001003C0001003C0001003D0001003C000101240001213C
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 812 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_0C value to
0x000101240001213C000101240001213C000101240001913C000180380000003C
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 813 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_0B value to
0x000040280000003C000004340000243C000004350000243C000004340000243C
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 814 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_0A value to
0x000004340000943C000080380001003C0001003C000140280001003C0001003C
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 815 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_09 value to
0x0001003D0001003C000101240001213C000101240001213C000101240001213C
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 816 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_08 value to
0x000101240001913C000180380000003C000040280000003C000004340000243C
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 817 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_07 value to
0x000004350000943C000080380001003C0001003C000140280001003C0001003C
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 818 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_06 value to
0x0001003D0001003C000101240001213C000101240001913C000180380000003C
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 819 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_05 value to
0x000040280000003C0000003C000004340000943D000080380001003C0001003C
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 820 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_04 value to
0x000140280001003C0001003C0001003D0001003C000101240001913C00018038
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 821 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_03 value to
0x0000003C000040280000003C0000003C000000340000943D000080380001003C
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 822 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_02 value to
0x0001003C000140280001003C0001003C0001003D000101240001913C00018038
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 823 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_01 value to
0x0000003C000040280000003C0000003C000000340000943D000080380001003C
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 824 - tcl is overriding PARAMETER C_CTRL_BRAM_INIT_00 value to
0x0001003C000140280001003C0001003C0001003D000101240001913C00018038
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 830 - tcl is overriding PARAMETER C_CTRL_BRAM_INITP_03 value to
0x0000000000000000000000000000000000000000000000000000000000000000
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 831 - tcl is overriding PARAMETER C_CTRL_BRAM_INITP_02 value to
0x0000000000000000000000000000000000000000000000020000000011100002
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 832 - tcl is overriding PARAMETER C_CTRL_BRAM_INITP_01 value to
0x0000000000020000000011100002000000000000000000001110000000000000
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 833 - tcl is overriding PARAMETER C_CTRL_BRAM_INITP_00 value to
0x0000000011100000000000000001110000000000000011100000000000001110
INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/xps_intc_v2_00_a/data/xps
_intc_v2_1_0.mpd line 78 - tcl is overriding PARAMETER C_NUM_INTR_INPUTS
value to 4
INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/xps_intc_v2_00_a/data/xps
_intc_v2_1_0.mpd line 79 - tcl is overriding PARAMETER C_KIND_OF_INTR value
to 0b00000000000000000000000000001100
INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/xps_intc_v2_00_a/data/xps
_intc_v2_1_0.mpd line 80 - tcl is overriding PARAMETER C_KIND_OF_EDGE value
to 0b00000000000000000000000000001100
INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/xps_intc_v2_00_a/data/xps
_intc_v2_1_0.mpd line 81 - tcl is overriding PARAMETER C_KIND_OF_LVL value to
0b00000000000000000000000000000010
Running system level update procedures...
Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
Running system level DRCs...
Performing System level DRCs on properties...
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
INFO: The DDR_SDRAM core has constraints automatically generated by XPS in
implementation/ddr_sdram_wrapper/ddr_sdram_wrapper.ucf.
It can be overridden by constraints placed in the system.ucf file.
INFO: The Ethernet_MAC core has constraints automatically generated by XPS in
implementation/ethernet_mac_wrapper/ethernet_mac_wrapper.ucf.
It can be overridden by constraints placed in the system.ucf file.
Modify defaults ...
Creating stub ...
Processing licensed instances ...
Completion time: 0.00 seconds
Creating hardware output directories ...
Managing hardware (BBD-specified) netlist files ...
IPNAME:xps_ethernetlite INSTANCE:ethernet_mac -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mhs line 163 -
Copying (BBD-specified) netlist files.
Managing cache ...
Elaborating instances ...
IPNAME:bram_block INSTANCE:lmb_bram -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mhs line 119 -
elaborating IP
Writing HDL for elaborated instances ...
Inserting wrapper level ...
Completion time: 1.00 seconds
Constructing platform-level connectivity ...
Completion time: 1.00 seconds
Writing (top-level) BMM ...
Writing (top-level and wrappers) HDL ...
Generating synthesis project file ...
Running XST synthesis ...
INFO:EDK:2502 - The following instances are synthesized with XST. The MPD option
IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
INSTANCE:microblaze_0 -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mhs line 52 -
Running XST synthesis
INSTANCE:mb_plb -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mhs line 79 -
Running XST synthesis
INSTANCE:ilmb -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mhs line 87 -
Running XST synthesis
INSTANCE:dlmb -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mhs line 94 -
Running XST synthesis
INSTANCE:dlmb_cntlr -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mhs line 101 -
Running XST synthesis
INSTANCE:ilmb_cntlr -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mhs line 110 -
Running XST synthesis
INSTANCE:lmb_bram -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mhs line 119 -
Running XST synthesis
INSTANCE:ddr_sdram -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mhs line 127 -
Running XST synthesis
INSTANCE:ethernet_mac -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mhs line 163 -
Running XST synthesis
INSTANCE:flash -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mhs line 183 -
Running XST synthesis
INSTANCE:rs232_uart -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mhs line 210 -
Running XST synthesis
INSTANCE:xps_timer_0 -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mhs line 226 -
Running XST synthesis
INSTANCE:clock_generator_0 -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mhs line 238 -
Running XST synthesis
INSTANCE:mdm_0 -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mhs line 262 -
Running XST synthesis
INSTANCE:proc_sys_reset_0 -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mhs line 275 -
Running XST synthesis
INSTANCE:xps_intc_0 -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mhs line 288 -
Running XST synthesis
Running NGCBUILD ...
IPNAME:ddr_sdram_wrapper INSTANCE:ddr_sdram -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mhs line 127 -
Running NGCBUILD
PMSPEC -- Overriding Xilinx file </opt/Xilinx/11.1/EDK/virtex4/data/virtex4.acd>
with local file </opt/Xilinx/11.1/ISE/virtex4/data/virtex4.acd>
Command Line: /opt/Xilinx/11.1/ISE/bin/lin64/unwrapped/ngcbuild -p
xc4vsx35ff668-10 -intstyle silent -uc ddr_sdram_wrapper.ucf -sd ..
ddr_sdram_wrapper.ngc ../ddr_sdram_wrapper.ngc
Reading NGO file
"/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/implementation/ddr_sdr
am_wrapper/ddr_sdram_wrapper.ngc" ...
Applying constraints in "ddr_sdram_wrapper.ucf" to the design...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../ddr_sdram_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 5 sec
Total CPU time to NGCBUILD completion: 4 sec
Writing NGCBUILD log file "../ddr_sdram_wrapper.blc"...
NGCBUILD done.
IPNAME:ethernet_mac_wrapper INSTANCE:ethernet_mac -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mhs line 163 -
Running NGCBUILD
PMSPEC -- Overriding Xilinx file </opt/Xilinx/11.1/EDK/virtex4/data/virtex4.acd>
with local file </opt/Xilinx/11.1/ISE/virtex4/data/virtex4.acd>
Command Line: /opt/Xilinx/11.1/ISE/bin/lin64/unwrapped/ngcbuild -p
xc4vsx35ff668-10 -intstyle silent -uc ethernet_mac_wrapper.ucf -sd ..
ethernet_mac_wrapper.ngc ../ethernet_mac_wrapper.ngc
Reading NGO file
"/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/implementation/etherne
t_mac_wrapper/ethernet_mac_wrapper.ngc" ...
Executing edif2ngd -noa "ethernetlite_v1_01_b_dmem_v2.edn"
"ethernetlite_v1_01_b_dmem_v2.ngo"
Release 11.1 - edif2ngd L.33 (lin64)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
INFO:NgdBuild - Release 11.1 edif2ngd L.33 (lin64)
INFO:NgdBuild - Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file </opt/Xilinx/11.1/EDK/data/edif2ngd.pfd> with
local file </opt/Xilinx/11.1/ISE/data/edif2ngd.pfd>
Writing module to "ethernetlite_v1_01_b_dmem_v2.ngo"...
Loading design module
"/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/implementation/etherne
t_mac_wrapper/ethernetlite_v1_01_b_dmem_v2.ngo"...
Applying constraints in "ethernet_mac_wrapper.ucf" to the design...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../ethernet_mac_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 7 sec
Total CPU time to NGCBUILD completion: 4 sec
Writing NGCBUILD log file "../ethernet_mac_wrapper.blc"...
NGCBUILD done.
IPNAME:rs232_uart_wrapper INSTANCE:rs232_uart -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mhs line 210 -
Running NGCBUILD
PMSPEC -- Overriding Xilinx file </opt/Xilinx/11.1/EDK/virtex4/data/virtex4.acd>
with local file </opt/Xilinx/11.1/ISE/virtex4/data/virtex4.acd>
Command Line: /opt/Xilinx/11.1/ISE/bin/lin64/unwrapped/ngcbuild -p
xc4vsx35ff668-10 -intstyle silent -sd .. rs232_uart_wrapper.ngc
../rs232_uart_wrapper.ngc
Reading NGO file
"/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/implementation/rs232_u
art_wrapper/rs232_uart_wrapper.ngc" ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../rs232_uart_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 2 sec
Total CPU time to NGCBUILD completion: 1 sec
Writing NGCBUILD log file "../rs232_uart_wrapper.blc"...
NGCBUILD done.
IPNAME:xps_intc_0_wrapper INSTANCE:xps_intc_0 -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mhs line 288 -
Running NGCBUILD
PMSPEC -- Overriding Xilinx file </opt/Xilinx/11.1/EDK/virtex4/data/virtex4.acd>
with local file </opt/Xilinx/11.1/ISE/virtex4/data/virtex4.acd>
Command Line: /opt/Xilinx/11.1/ISE/bin/lin64/unwrapped/ngcbuild -p
xc4vsx35ff668-10 -intstyle silent -sd .. xps_intc_0_wrapper.ngc
../xps_intc_0_wrapper.ngc
Reading NGO file
"/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/implementation/xps_int
c_0_wrapper/xps_intc_0_wrapper.ngc" ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../xps_intc_0_wrapper.ngc" ...
Total REAL time to NGCBUILD completion: 2 sec
Total CPU time to NGCBUILD completion: 2 sec
Writing NGCBUILD log file "../xps_intc_0_wrapper.blc"...
NGCBUILD done.
Rebuilding cache ...
Total run time: 434.00 seconds
Running synthesis...
bash -c "cd synthesis; ./synthesis.sh"
xst -ifn system_xst.scr -intstyle silent
Running XST synthesis ...
XST completed
Release 11.1 - ngcbuild L.33 (lin64)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
Overriding Xilinx file <ngcflow.csf> with local file
</opt/Xilinx/11.1/ISE/data/ngcflow.csf>
Command Line: /opt/Xilinx/11.1/ISE/bin/lin64/unwrapped/ngcbuild ./system.ngc
../implementation/system.ngc -sd ../implementation -i -ise
../__xps/ise/system.ise
Reading NGO file
"/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/synthesis/system.ngc"
...
Loading design module "../implementation/microblaze_0_wrapper.ngc"...
Loading design module "../implementation/mb_plb_wrapper.ngc"...
Loading design module "../implementation/ilmb_wrapper.ngc"...
Loading design module "../implementation/dlmb_wrapper.ngc"...
Loading design module "../implementation/dlmb_cntlr_wrapper.ngc"...
Loading design module "../implementation/ilmb_cntlr_wrapper.ngc"...
Loading design module "../implementation/lmb_bram_wrapper.ngc"...
Loading design module "../implementation/ddr_sdram_wrapper.ngc"...
Loading design module "../implementation/ethernet_mac_wrapper.ngc"...
Loading design module "../implementation/flash_wrapper.ngc"...
Loading design module "../implementation/rs232_uart_wrapper.ngc"...
Loading design module "../implementation/xps_timer_0_wrapper.ngc"...
Loading design module "../implementation/clock_generator_0_wrapper.ngc"...
Loading design module "../implementation/mdm_0_wrapper.ngc"...
Loading design module "../implementation/proc_sys_reset_0_wrapper.ngc"...
Loading design module "../implementation/xps_intc_0_wrapper.ngc"...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGCBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGC file "../implementation/system.ngc" ...
Total REAL time to NGCBUILD completion: 8 sec
Total CPU time to NGCBUILD completion: 8 sec
Writing NGCBUILD log file "../implementation/system.blc"...
NGCBUILD done.
*********************************************
Running Xilinx Implementation tools..
*********************************************
xflow -wd implementation -p xc4vsx35ff668-10 -implement xflow.opt -ise
../__xps/ise/system.ise system.ngc
Release 11.1 - Xflow L.33 (lin64)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
xflow -wd implementation -p xc4vsx35ff668-10 -implement xflow.opt -ise
../__xps/ise/system.ise system.ngc
PMSPEC -- Overriding Xilinx file </opt/Xilinx/11.1/EDK/virtex4/data/virtex4.acd>
with local file </opt/Xilinx/11.1/ISE/virtex4/data/virtex4.acd>
.... Copying flowfile /opt/Xilinx/11.1/ISE/xilinx/data/fpga.flw into working
directory
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/implementation
Using Flow File:
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/implementation/fpga.flw
Using Option File(s):
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/implementation/xflow.o
pt
Creating Script File ...
#----------------------------------------------#
# Starting program ngdbuild
# ngdbuild -ise ../__xps/ise/system.ise -p xc4vsx35ff668-10 -nt timestamp -bm
system.bmm
"/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/implementation/system.
ngc" -uc system.ucf system.ngd
#----------------------------------------------#
Release 11.1 - ngdbuild L.33 (lin64)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file </opt/Xilinx/11.1/EDK/virtex4/data/virtex4.acd>
with local file </opt/Xilinx/11.1/ISE/virtex4/data/virtex4.acd>
Command Line: /opt/Xilinx/11.1/ISE/bin/lin64/unwrapped/ngdbuild -ise
../__xps/ise/system.ise -p xc4vsx35ff668-10 -nt timestamp -bm system.bmm
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/implementation/system.n
gc -uc system.ucf system.ngd
Reading NGO file
"/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/implementation/system.
ngc" ...
Gathering constraint information from source properties...
Done.
Applying constraints in "system.ucf" to the design...
Resolving constraint associations...
Checking Constraint Associations...
INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
'TS_sys_clk_pin', was traced into DCM_ADV instance
clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST.
The following new TNM groups and period specifications were generated at the
DCM_ADV output(s):
CLK0: <TIMESPEC
TS_clock_generator_0_clock_generator_0_Using_DCM0_DCM0_INST_CLK0 = PERIOD
"clock_generator_0_clock_generator_0_Using_DCM0_DCM0_INST_CLK0"
TS_sys_clk_pin HIGH 50%>
INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
'TS_sys_clk_pin', was traced into DCM_ADV instance
clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST.
The following new TNM groups and period specifications were generated at the
DCM_ADV output(s):
CLK90: <TIMESPEC
TS_clock_generator_0_clock_generator_0_Using_DCM0_DCM0_INST_CLK90 = PERIOD
"clock_generator_0_clock_generator_0_Using_DCM0_DCM0_INST_CLK90"
TS_sys_clk_pin PHASE 2.5 ns HIGH 50%>
Done...
Checking Partitions ...
Processing BMM file ...
Checking expanded design ...
WARNING:NgdBuild:443 - SFF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/COLLISION_SYNC' has unconnected
output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU10'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU15'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU20'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU25'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU30'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU35'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU130'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU237'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU10'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU15'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU20'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU25'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU30'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU35'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU130'
has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU237'
has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'FLASH/FLASH/EMC_CTRL_I/MEM_STATE_MACHINE_I/READ_COMPLETE_PIPE_GEN[6].READ_CO
MPLETE_PIPE' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'FLASH/FLASH/EMC_CTRL_I/MEM_STEER_I/ASYNC_MEM_RDACK_GEN.AALIGN_PIPE_GEN[1].AA
LIGN_PIPE' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'FLASH/FLASH/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTAC
HMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[0].I_SIZE_S_H_R
EG' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'FLASH/FLASH/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTAC
HMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG
' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'FLASH/FLASH/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTAC
HMENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[3].I_FDRSE_BE0t
o3' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'FLASH/FLASH/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTAC
HMENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[2].I_FDRSE_BE0t
o3' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'FLASH/FLASH/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTAC
HMENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[1].I_FDRSE_BE0t
o3' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'FLASH/FLASH/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTAC
HMENT/I_BUS_ADDRESS_COUN
TER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[0].I_FDRSE_BE0t
o3' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'FLASH/FLASH/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTAC
HMENT/I_BURST_SUPPORT/CONTROL_DBEAT_CNTR_I/STRUCTURAL_A_GEN.I_ADDSUB_GEN[5].F
DRE_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'FLASH/FLASH/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTAC
HMENT/I_BURST_SUPPORT/RESPONSE_DBEAT_CNTR_I/STRUCTURAL_A_GEN.I_ADDSUB_GEN[5].
FDRE_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'FLASH/FLASH/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTAC
HMENT/I_DECODER/GEN_CE_FOR_SHARED.GEN_BKEND_CE_REGISTERS[0].I_BKEND_RDCE_REG'
has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'FLASH/FLASH/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTAC
HMENT/I_DECODER/GEN_CE_FOR_SHARED.GEN_BKEND_CE_REGISTERS[0].I_BKEND_WRCE_REG'
has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[0].TCSR0_FF
_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[1].TCSR0_FF
_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[2].TCSR0_FF
_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[3].TCSR0_FF
_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[4].TCSR0_FF
_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[5].TCSR0_FF
_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[6].TCSR0_FF
_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[7].TCSR0_FF
_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[8].TCSR0_FF
_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[9].TCSR0_FF
_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[10].TCSR0_F
F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[11].TCSR0_F
F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[12].TCSR0_F
F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[13].TCSR0_F
F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[14].TCSR0_F
F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[15].TCSR0_F
F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[16].TCSR0_F
F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[17].TCSR0_F
F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[18].TCSR0_F
F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[19].TCSR0_F
F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[20].TCSR0_F
F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[0].TCSR1_FF
_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[1].TCSR1_FF
_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[2].TCSR1_FF
_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[3].TCSR1_FF
_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[4].TCSR1_FF
_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[5].TCSR1_FF
_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[6].TCSR1_FF
_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[7].TCSR1_FF
_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[8].TCSR1_FF
_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[9].TCSR1_FF
_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[10].TCSR1_F
F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[11].TCSR1_F
F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[12].TCSR1_F
F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[13].TCSR1_F
F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[14].TCSR1_F
F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[15].TCSR1_F
F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[16].TCSR1_F
F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[17].TCSR1_F
F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[18].TCSR1_F
F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[19].TCSR1_F
F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'xps_timer_0/xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[20].TCSR1_F
F_I' has unconnected output pin
WARNING:NgdBuild:452 - logical net 'N106' has no driver
WARNING:NgdBuild:452 - logical net 'N107' has no driver
WARNING:NgdBuild:452 - logical net 'N108' has no driver
WARNING:NgdBuild:452 - logical net 'N109' has no driver
WARNING:NgdBuild:452 - logical net 'N110' has no driver
WARNING:NgdBuild:452 - logical net 'N111' has no driver
WARNING:NgdBuild:452 - logical net 'N112' has no driver
WARNING:NgdBuild:452 - logical net 'N113' has no driver
WARNING:NgdBuild:452 - logical net 'N114' has no driver
WARNING:NgdBuild:452 - logical net 'N115' has no driver
WARNING:NgdBuild:452 - logical net 'N116' has no driver
WARNING:NgdBuild:452 - logical net 'N117' has no driver
WARNING:NgdBuild:452 - logical net 'N118' has no driver
WARNING:NgdBuild:452 - logical net 'N119' has no driver
WARNING:NgdBuild:452 - logical net 'N120' has no driver
WARNING:NgdBuild:452 - logical net 'N121' has no driver
WARNING:NgdBuild:452 - logical net 'N122' has no driver
WARNING:NgdBuild:452 - logical net 'N123' has no driver
WARNING:NgdBuild:452 - logical net 'N124' has no driver
WARNING:NgdBuild:452 - logical net 'N125' has no driver
WARNING:NgdBuild:452 - logical net 'N126' has no driver
WARNING:NgdBuild:452 - logical net 'N127' has no driver
WARNING:NgdBuild:452 - logical net 'N128' has no driver
WARNING:NgdBuild:452 - logical net 'N129' has no driver
WARNING:NgdBuild:452 - logical net 'N130' has no driver
WARNING:NgdBuild:452 - logical net 'N131' has no driver
WARNING:NgdBuild:452 - logical net 'N132' has no driver
WARNING:NgdBuild:452 - logical net 'N133' has no driver
WARNING:NgdBuild:452 - logical net 'N134' has no driver
WARNING:NgdBuild:452 - logical net 'N135' has no driver
WARNING:NgdBuild:452 - logical net 'N136' has no driver
WARNING:NgdBuild:452 - logical net 'N137' has no driver
WARNING:NgdBuild:452 - logical net 'N70' has no driver
WARNING:NgdBuild:452 - logical net 'N71' has no driver
WARNING:NgdBuild:452 - logical net 'N72' has no driver
WARNING:NgdBuild:452 - logical net 'N73' has no driver
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 107
Writing NGD file "system.ngd" ...
Total REAL time to NGDBUILD completion: 18 sec
Total CPU time to NGDBUILD completion: 17 sec
Writing NGDBUILD log file "system.bld"...
NGDBUILD done.
#----------------------------------------------#
# Starting program map
# map -ise ../__xps/ise/system.ise -o system_map.ncd -pr b -ol high -timing
system.ngd system.pcf
#----------------------------------------------#
Release 11.1 - Map L.33 (lin64)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file </opt/Xilinx/11.1/EDK/data/Xdh_PrimTypeLib.xda>
with local file </opt/Xilinx/11.1/ISE/data/Xdh_PrimTypeLib.xda>
Using target part "4vsx35ff668-10".
WARNING:LIT:243 - Logical network N106 has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 705
more times for the following (max. 5 shown):
N107,
N108,
N109,
N110,
N111
To see the details of these warning messages, please use the -detail switch.
Mapping design into LUTs...
WARNING:MapLib:701 - Signal fpga_0_Ethernet_MAC_PHY_col_pin connected to top
level port fpga_0_Ethernet_MAC_PHY_col_pin has been removed.
WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFG symbol
"fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP/BUFG" (output
signal=fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP) has a mix of clock and
non-clock loads. The non-clock loads are:
Pin D of Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/phy_tx_clk_d1
Writing file system_map.ngm...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
Running timing-driven placement...
Total REAL time at the beginning of Placer: 39 secs
Total CPU time at the beginning of Placer: 36 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:9617684e) REAL time: 45 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:9617684e) REAL time: 46 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:2d2ee4ac) REAL time: 46 secs
Phase 4.2 Initial Clock and IO Placement
Phase 4.2 Initial Clock and IO Placement (Checksum:870f94f1) REAL
time: 49 secs
Phase 5.30 Global Clock Region Assignment
Phase 5.30 Global Clock Region Assignment (Checksum:870f94f1) REAL
time: 49 secs
Phase 6.3 Local Placement Optimization
Phase 6.3 Local Placement Optimization (Checksum:870f94f1) REAL time: 49 secs
Phase 7.5 Local Placement Optimization
Phase 7.5 Local Placement Optimization (Checksum:870f94f1) REAL time: 49 secs
Phase 8.8 Global Placement
.....................
........
........
....................
..................
...........
.........................
............
.....
...............
..............
...........
..................
............
...............
.................
............
...........
...
.........
................
.....................
...
.....
..............
..............
..................
........
........
...............
...................
..................
Phase 8.8 Global Placement (Checksum:244a9b19) REAL time: 2 mins 35 secs
Phase 9.5 Local Placement Optimization
Phase 9.5 Local Placement Optimization (Checksum:244a9b19) REAL time:
2 mins 36 secs
Phase 10.18 Placement Optimization
Phase 10.18 Placement Optimization (Checksum:210c4081) REAL time: 7
mins 31 secs
Phase 11.5 Local Placement Optimization
Phase 11.5 Local Placement Optimization (Checksum:210c4081) REAL
time: 7 mins 32 secs
Phase 12.34 Placement Validation
Phase 12.34 Placement Validation (Checksum:210c4081) REAL time: 7 mins 32 secs
Total REAL time to Placer completion: 7 mins 34 secs
Total CPU time to Placer completion: 7 mins 27 secs
Running post-placement packing...
Design Summary:
Number of errors: 0
Number of warnings: 23
Logic Utilization:
Number of Slice Flip Flops: 6,004 out of 30,720 19%
Number of 4 input LUTs: 7,538 out of 30,720 24%
Logic Distribution:
Number of occupied Slices: 6,322 out of 15,360 41%
Number of Slices containing only related logic: 6,322 out of 6,322 100%
Number of Slices containing unrelated logic: 0 out of 6,322 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 7,718 out of 30,720 25%
Number used as logic: 6,747
Number used as a route-thru: 180
Number used as 16x1 RAMs: 4
Number used for Dual Port RAMs: 658
(Two LUTs used per Dual Port RAM)
Number used as Shift registers: 129
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
Number of bonded IOBs:
138 out of 448 30%
IOB Flip Flops: 253
IOB Dual-Data Rate Flops: 74
Number of BUFG/BUFGCTRLs: 6 out of 32 18%
Number used as BUFGs: 6
Number of FIFO16/RAMB16s: 24 out of 192 12%
Number used as RAMB16s: 24
Number of DSP48s: 3 out of 192 1%
Number of DCM_ADVs: 1 out of 8 12%
Number of BSCAN_VIRTEX4s: 1 out of 4 25%
Number of IDELAYCTRLs: 2 out of 16 12%
Average Fanout of Non-Clock Nets: 3.45
Peak Memory Usage: 858 MB
Total REAL time to MAP completion: 7 mins 44 secs
Total CPU time to MAP completion: 7 mins 37 secs
Mapping completed.
See MAP report file "system_map.mrp" for details.
#----------------------------------------------#
# Starting program par
# par -ise ../__xps/ise/system.ise -w -ol high system_map.ncd system.ncd
system.pcf
#----------------------------------------------#
Release 11.1 - par L.33 (lin64)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file
</opt/Xilinx/11.1/EDK/data/parBmgr.acd> with local file
</opt/Xilinx/11.1/ISE/data/parBmgr.acd>
Constraints file: system.pcf.
Loading device for application Rf_Device from file '4vsx35.nph' in environment
/opt/Xilinx/11.1/ISE:/opt/Xilinx/11.1/EDK.
"system" is an NCD, version 3.2, device xc4vsx35, package ff668, speed -10
This design is using the default stepping level (major silicon
revision) for this device (1). Unless your design is
targeted at devices of this stepping level, it is recommended that you
explicitly specify the stepping level of the
parts you will be using. This will allow the tools to take advantage
of any available performance and functional
enhancements for this device. The latest stepping level for this
device is '2'. Additional information on "stepping
level" is available at support.xilinx.com.
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to
85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.69 2009-03-03".
Device Utilization Summary:
Number of BSCANs 1 out of 4 25%
Number of BUFGs 6 out of 32 18%
Number of DCM_ADVs 1 out of 8 12%
Number of DSP48s 3 out of 192 1%
Number of IDELAYCTRLs 2 out of 16 12%
Number of LOCed IDELAYCTRLs 2 out of 2 100%
Number of ILOGICs 72 out of 448 16%
Number of External IOBs 138 out of 448 30%
Number of LOCed IOBs 138 out of 138 100%
Number of OLOGICs 124 out of 448 27%
Number of RAMB16s 24 out of 192 12%
Number of Slices 6322 out of 15360 41%
Number of SLICEMs 436 out of 7680 5%
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 17 secs
Finished initial
Timing Analysis. REAL time: 17 secs
WARNING:Par:288 - The signal ilmb_LMB_ABus<10> has no load. PAR will
not attempt to route this signal.
WARNING:Par:288 - The signal ilmb_LMB_ABus<30> has no load. PAR will
not attempt to route this signal.
WARNING:Par:288 - The signal ilmb_LMB_ABus<14> has no load. PAR will
not attempt to route this signal.
WARNING:Par:288 - The signal ilmb_LMB_ABus<17> has no load. PAR will
not attempt to route this signal.
WARNING:Par:288 - The signal ilmb_LMB_ABus<3> has no load. PAR will
not attempt to route this signal.
WARNING:Par:288 - The signal ilmb_LMB_ABus<31> has no load. PAR will
not attempt to route this signal.
WARNING:Par:288 - The signal ilmb_LMB_ABus<4> has no load. PAR will
not attempt to route this signal.
WARNING:Par:288 - The signal ilmb_LMB_ABus<13> has no load. PAR will
not attempt to route this signal.
WARNING:Par:288 - The signal ilmb_LMB_ABus<7> has no load. PAR will
not attempt to route this signal.
WARNING:Par:288 - The signal ilmb_LMB_ABus<16> has no load. PAR will
not attempt to route this signal.
WARNING:Par:288 - The signal ilmb_LMB_ABus<2> has no load. PAR will
not attempt to route this signal.
WARNING:Par:288 - The signal ilmb_LMB_ABus<6> has no load. PAR will
not attempt to route this signal.
WARNING:Par:288 - The signal ilmb_LMB_ABus<18> has no load. PAR will
not attempt to route this signal.
WARNING:Par:288 - The signal ilmb_LMB_ABus<11> has no load. PAR will
not attempt to route this signal.
WARNING:Par:288 - The signal ilmb_LMB_ABus<15> has no load. PAR will
not attempt to route this signal.
WARNING:Par:288 - The signal ilmb_LMB_ABus<9> has no load. PAR will
not attempt to route this signal.
WARNING:Par:288 - The signal ilmb_LMB_ABus<12> has no load. PAR will
not attempt to route this signal.
WARNING:Par:288 - The signal ilmb_LMB_ABus<8> has no load. PAR will
not attempt to route this signal.
WARNING:Par:288 - The signal ilmb_LMB_ABus<1> has no load. PAR will
not attempt to route this signal.
Starting Router
Phase 1 : 45481 unrouted; REAL time: 19 secs
Phase 2 : 38170 unrouted; REAL time: 20 secs
Phase 3 : 13618 unrouted; REAL time: 27 secs
Phase 4 : 14075 unrouted; (Setup:0, Hold:0, Component Switching
Limit:0) REAL time: 38 secs
Updating file: system.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:5970, Hold:0, Component Switching
Limit:0) REAL time: 1 mins 3 secs
Phase 6 : 0 unrouted; (Setup:3213, Hold:0, Component Switching
Limit:0) REAL time: 2 mins 25 secs
Updating file: system.ncd with current fully routed design.
Phase 7 : 0 unrouted; (Setup:3213, Hold:0, Component Switching
Limit:0) REAL time: 3 mins 6 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)
REAL time: 6 mins 49 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)
REAL time: 6 mins 49 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)
REAL time: 6 mins 57 secs
Total REAL time to Router completion: 6 mins 57 secs
Total CPU time to Router completion: 6 mins 52 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk_100_0000MHzDCM0 | BUFGCTRL_X0Y2| No | 5213 | 0.651 | 3.145 |
+---------------------+--------------+------+------+------------+-------------+
|fpga_0_Ethernet_MAC_ | | | | | |
|PHY_tx_clk_pin_BUFGP | | | | | |
| |BUFGCTRL_X0Y31| No | 23 | 0.038 | 2.890 |
+---------------------+--------------+------+------+------------+-------------+
| mdm_0/Dbg_Clk_1 |BUFGCTRL_X0Y29| No | 154 | 0.441 | 2.993 |
+---------------------+--------------+------+------+------------+-------------+
|fpga_0_Ethernet_MAC_ | | | | | |
|PHY_rx_clk_pin_BUFGP | | | | | |
| |BUFGCTRL_X0Y30| No | 22 | 0.093 | 2.910 |
+---------------------+--------------+------+------+------------+-------------+
|clk_100_0000MHz90DCM | | | | | |
| 0 | BUFGCTRL_X0Y1| No | 50 | 0.122 | 3.059 |
+---------------------+--------------+------+------+------------+-------------+
| clk_200_0000MHz | BUFGCTRL_X0Y0| No | 2 | 0.019 | 2.962 |
+---------------------+--------------+------+------+------------+-------------+
| mdm_0/Dbg_Update_1 | Local| | 33 | 1.908 | 2.932 |
+---------------------+--------------+------+------+------------+-------------+
|fpga_0_clk_1_sys_clk | | | | | |
| _pin_IBUFG | Local| | 6 | 0.085 | 1.328 |
+---------------------+--------------+------+---
---+------------+-------------+
|RS232_Uart_Interrupt | | | | | |
| | Local| | 1 | 0.000 | 0.530 |
+---------------------+--------------+------+------+------------+-------------+
|Ethernet_MAC_IP2INTC | | | | | |
| _Irpt | Local| | 1 | 0.000 | 1.337 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case
| Best Case | Timing | Timing
| | Slack
| Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_clock_generator_0_clock_generator_0_Us | SETUP |
0.157ns| 9.843ns| 0| 0
ing_DCM0_DCM0_INST_CLK0 = PERIOD | HOLD |
0.112ns| | 0| 0
TIMEGRP "clock_generator_0_clock_ | |
| | |
generator_0_Using_DCM0_DCM0_INST_CLK0" | |
| | |
TS_sys_clk_pin HIGH 50% | |
| | |
------------------------------------------------------------------------------------------------------
TSRXIN_Ethernet_MAC = MAXDELAY FROM TIMEG | MAXDELAY |
0.404ns| 5.596ns| 0| 0
RP "PADS" TO TIMEGRP "RXCLK_GRP_E | |
| | |
thernet_MAC" 6 ns | |
| | |
------------------------------------------------------------------------------------------------------
TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | SETUP |
8.656ns| 1.344ns| 0| 0
pin" 100 MHz HIGH 50% | HOLD |
0.549ns| | 0| 0
| MINLOWPULSE |
4.666ns| 5.334ns| 0| 0
------------------------------------------------------------------------------------------------------
TS_clock_generator_0
_clock_generator_0_Us | SETUP | 2.926ns| 6.098ns|
0| 0
ing_DCM0_DCM0_INST_CLK90 = PERIOD | HOLD |
0.548ns| | 0| 0
TIMEGRP "clock_generator_0_clock | |
| | |
_generator_0_Using_DCM0_DCM0_INST_CLK90" | |
| | |
TS_sys_clk_pin PHASE 2.5 ns HIGH | |
| | |
50% | |
| | |
------------------------------------------------------------------------------------------------------
NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_B | NETSKEW |
4.229ns| 0.771ns| 0| 0
UFGP" MAXSKEW = 5 ns | |
| | |
------------------------------------------------------------------------------------------------------
NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_B | NETSKEW |
4.343ns| 0.657ns| 0| 0
UFGP" MAXSKEW = 5 ns | |
| | |
------------------------------------------------------------------------------------------------------
TSTXOUT_Ethernet_MAC = MAXDELAY FROM TIME | MAXDELAY |
5.862ns| 4.138ns| 0| 0
GRP "TXCLK_GRP_Ethernet_MAC" TO T | |
| | |
IMEGRP "PADS" 10 ns | |
| | |
------------------------------------------------------------------------------------------------------
NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_B | SETUP |
10.041ns| 11.311ns| 0| 0
UFGP" PERIOD = 40 ns HIGH 14 ns | HOLD |
0.646ns| | 0| 0
------------------------------------------------------------------------------------------------------
NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_B | SETUP |
23.259ns| 5.414ns| 0| 0
UFGP" PERIOD = 40 ns HIGH 14 ns | HOLD |
0.546ns| | 0| 0
------------------------------------------------------------------------------------------------------
Derived Constraint Report
Derived Constraints for TS_sys_clk_pin
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period
| Timing Errors | Paths Analyzed |
| Constraint | Requirement
|-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct |
Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_sys_clk_pin | 10.000ns| 5.334ns|
9.843ns| 0| 0| 4| 5894613|
| TS_clock_generator_0_clock_gen| 10.000ns| 9.843ns|
N/A| 0| 0| 5894433| 0|
| erator_0_Using_DCM0_DCM0_INST_| | |
| | | | |
| CLK0 | | |
| | | | |
| TS_clock_generator_0_clock_gen| 10.000ns| 6.098ns|
N/A| 0| 0| 180| 0|
| erator_0_Using_DCM0_DCM0_INST_| | |
| | | | |
| CLK90 | | |
| | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 19 loadless signals in this design. This
design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 7 mins 5 secs
Total CPU time to PAR completion: 7 mins
Peak Memory Usage: 694 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 21
Number of info messages: 0
Writing design to file system.ncd
PAR done!
#----------------------------------------------#
# Starting program post_par_trce
# trce -ise ../__xps/ise/system.ise -e 3 -xml system.twx system.ncd system.pcf
#----------------------------------------------#
Release 11.1 - Trace (lin64)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file </opt/Xilinx/11.1/EDK/virtex4/data/virtex4.acd>
with local file </opt/Xilinx/11.1/ISE/virtex4/data/virtex4.acd>
Loading device for application Rf_Device from file '4vsx35.nph' in environment
/opt/Xilinx/11.1/ISE:/opt/Xilinx/11.1/EDK.
"system" is an NCD, version 3.2, device xc4vsx35, package ff668, speed -10
This design is using the default stepping level (major silicon revision) for
this device (1). Unless your design is targeted at devices of this stepping
level, it is recommended that you explicitly specify the stepping level of the
parts you will be using. This will allow the tools to take advantage of any
available performance and functional enhancements for this device. The latest
stepping level for this device is '2'. Additional information on "stepping
level" is available at support.xilinx.com.
--------------------------------------------------------------------------------
Release 11.1 Trace (lin64)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
/opt/Xilinx/11.1/ISE/bin/lin64/unwrapped/trce -ise ../__xps/ise/system.ise -e 3
-xml system.twx system.ncd system.pcf
Design file: system.ncd
Physical constraint file: system.pcf
Device,speed: xc4vsx35,-10 (PRODUCTION 1.69 2009-03-03, STEPPING
level 1)
Report level: error report
--------------------------------------------------------------------------------
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a
50 Ohm transmission line loading model. For the details of this model, and
for more information on accounting for different loading conditions, please
see the device datasheet.
Timing summary:
---------------
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
Constraints cover 5894888 paths, 2 nets, and 42644 connections
Design statistics:
Minimum period: 11.311ns (Maximum frequency: 88.410MHz)
Maximum path delay from/to any node: 5.596ns
Maximum net skew: 0.771ns
Analysis completed Thu Jun 18 22:06:44 2009
--------------------------------------------------------------------------------
Generating Report ...
Number of warnings: 0
Number of info messages: 2
Total time: 28 secs
xflow done!
touch __xps/system_routed
xilperl /opt/Xilinx/11.1/EDK/data/fpga_impl/observe_par.pl -error yes
implementation/system.par
Analyzing implementation/system.par
*********************************************
Running Bitgen..
*********************************************
cd implementation; bitgen -w -f bitgen.ut system; cd ..
Release 11.1 - Bitgen L.33 (lin64)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file </opt/Xilinx/11.1/EDK/virtex4/data/virtex4.acd>
with local file </opt/Xilinx/11.1/ISE/virtex4/data/virtex4.acd>
Loading device for application Rf_Device from file '4vsx35.nph' in environment
/opt/Xilinx/11.1/ISE:/opt/Xilinx/11.1/EDK.
"system" is an NCD, version 3.2, device xc4vsx35, package ff668, speed -10
This design is using the default stepping level (major silicon revision) for
this device (1). Unless your design is targeted at devices of this stepping
level, it is recommended that you explicitly specify the stepping level of the
parts you will be using. This will allow the tools to take advantage of any
available performance and functional enhancements for this device. The latest
stepping level for this device is '2'. Additional information on "stepping
level" is available at support.xilinx.com.
Opened constraints file system.pcf.
Thu Jun 18 22:06:54 2009
INFO:Data2MEM:100 - BRAM 'lmb_bram/lmb_bram/ramb16_0' updated to
placement 'RAMB16_X4Y14' from design.
INFO:Data2MEM:100 - BRAM 'lmb_bram/lmb_bram/ramb16_1' updated to
placement 'RAMB16_X5Y16' from design.
INFO:Data2MEM:100 - BRAM 'lmb_bram/lmb_bram/ramb16_2' updated to
placement 'RAMB16_X4Y16' from design.
INFO:Data2MEM:100 - BRAM 'lmb_bram/lmb_bram/ramb16_3' updated to
placement 'RAMB16_X4Y15' from design.
Running DRC.
WARNING:PhysDesignRules:367 - The signal <ilmb_LMB_ABus<10>> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ilmb_LMB_ABus<30>> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ilmb_LMB_ABus<14>> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ilmb_LMB_ABus<17>> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ilmb_LMB_ABus<3>> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ilmb_LMB_ABus<31>> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ilmb_LMB_ABus<4>> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ilmb_LMB_ABus<13>> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ilmb_LMB_ABus<7>> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ilmb_LMB_ABus<16>> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ilmb_LMB_ABus<2>> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ilmb_LMB_ABus<6>> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ilmb_LMB_ABus<18>> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ilmb_LMB_ABus<11>> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ilmb_LMB_ABus<15>> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ilmb_LMB_ABus<9>> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ilmb_LMB_ABus<12>> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ilmb_LMB_ABus<8>> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ilmb_LMB_ABus<1>> is incomplete. The
signal does not drive any load pins in the design.
DRC detected 0 errors and 19 warnings. Please see the previously displayed
individual error or warning messages for more details.
Creating bit map...
Saving bit stream in "system.bit".
Bitstream generation is complete.
Done!
At Local date and time: Fri Jun 19 10:05:30 2009
make -f system.make libs started...
*********************************************
Creating software libraries...
*********************************************
libgen -mhs system.mhs -p xc4vsx35ff668-10 -lp
/home/users/nicolas/research/SoPC/OS/petalinux-svn/hardware/edk_user_repository/
-msg __xps/ise/xmsgprops.lst system.mss
W
libgen
Xilinx EDK 11.1 Build EDK_L.29.1
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
ARNING:EDK - INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable
is set to '/opt/Xilinx/11.1/Xilinx.lic'.
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
'5280@xxxxxxxxxxxx'.
INFO:Security:66 - Your license for 'SDK' is for evaluation use only.
WARNING:Security:43 - No license file was found in the standard Xilinx
license directory.
WARNING:Security:44 - No license file was found.
Please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
WARNING:Security:40 - Your license for 'SDK' expires in 7 days.
Command Line: libgen -mhs system.mhs -p xc4vsx35ff668-10 -lp
/home/users/nicolas/research/SoPC/OS/petalinux-svn/hardware/edk_user_repository/
-msg __xps/ise/xmsgprops.lst system.mss
Release 11.1 - psf2Edward EDK_L.29.1 (lin64)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
Checking platform configuration ...
IPNAME:plb_v46 INSTANCE:mb_plb -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mhs line 79 - 2
master(s) : 6 slave(s)
IPNAME:lmb_v10 INSTANCE:ilmb -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mhs line 87 - 1
master(s) : 1 slave(s)
IPNAME:lmb_v10 INSTANCE:dlmb -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mhs line 94 - 1
master(s) : 1 slave(s)
Checking port drivers...
WARNING:EDK:2098 - PORT:IWAIT CONNECTOR:ilmb_LMB_Wait -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_20_a/data/m
icroblaze_v2_1_0.mpd line 234 - No driver found. Port will be driven to GND!
WARNING:EDK:2098 - PORT:DWAIT CONNECTOR:dlmb_LMB_Wait -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_20_a/data/m
icroblaze_v2_1_0.mpd line 270 - No driver found. Port will be driven to GND!
WARNING:EDK:2098 - PORT:bscan_tdo1 CONNECTOR:bscan_tdo1 -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_
e/data/mdm_v2_1
_0.mpd line 230 - No driver found. Port will be driven to GND!
WARNING:EDK:2099 - PORT:I_ADDRTAG CONNECTOR:ilmb_M_ADDRTAG -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_20_a/data/m
icroblaze_v2_1_0.mpd line 232 - floating connection!
WARNING:EDK:2099 - PORT:D_ADDRTAG CONNECTOR:dlmb_M_ADDRTAG -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_20_a/data/m
icroblaze_v2_1_0.mpd line 273 - floating connection!
WARNING:EDK:2099 - PORT:bscan_tdi CONNECTOR:bscan_tdi -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_e/data/mdm_v2_1
_0.mpd line 223 - floating connection!
WARNING:EDK:2099 - PORT:bscan_reset CONNECTOR:bscan_reset -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_e/data/mdm_v2_1
_0.mpd line 224 - floating connection!
WARNING:EDK:2099 - PORT:bscan_shift CONNECTOR:bscan_shift -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_e/data/mdm_v2_1
_0.mpd line 225 - floating connection!
WARNING:EDK:2099 - PORT:bscan_update CONNECTOR:bscan_update -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_e/data/mdm_v2_1
_0.mpd line 226 - floating connection!
WARNING:EDK:2099 - PORT:bscan_capture CONNECTOR:bscan_capture -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_e/data/mdm_v2_1
_0.mpd line 227 - floating connection!
WARNING:EDK:2099 - PORT:bscan_sel1 CONNECTOR:bscan_sel1 -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_e/data/mdm_v2_1
_0.mpd line 228 - floating connection!
WARNING:EDK:2099 - PORT:bscan_drck1 CONNECTOR:bscan_drck1 -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_e/data/mdm_v2_1
_0.mpd line 229 - floating connection!
Performing Clock DRCs...
Performing Reset DRCs...
Overriding system level properties...
Running system level update procedures...
Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
Running system level DRCs...
Performing System level DRCs on properties...
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
INFO:EDK:2497 - The following PARAMETERs of os petalinux are ignored as
PARAMETER microblaze_exceptions has a default value "false"
WARNING:EDK:473 -
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/system.mss line 14 -
Ignoring PARAMETER microblaze_exception_vectors ...
INFO:EDK:1740 - List of peripherals connected to processor instance
microblaze_0:
- DDR_SDRAM
- Ethernet_MAC
- FLASH
- RS232_Uart
- dlmb_cntlr
- ilmb_cntlr
- mdm_0
- xps_intc_0
- xps_timer_0
-- Generating libraries for processor: microblaze_0 --
Staging source files.
Running DRCs.
#--------------------------------------
# PetaLogix / PetaLinux BSP DRC...!
#--------------------------------------
Running generate.
#--------------------------------------
# PetaLinux BSP generate...
#--------------------------------------
ERROR:EDK:3234 - request for property: handletype of a MODULE not handled.
ERROR:EDK:3234 - request for property: handletype of a MODULE not handled.
ERROR:EDK:3234 - request for property: handletype of a MODULE not handled.
ERROR:EDK:3234 - request for property: handletype of a MODULE not handled.
Calling standalone::generate
Running post_generate.
Running include - 'gmake -s include "COMPILER=mb-gcc" "ARCHIVER=mb-ar"
"COMPILER_FLAGS=-mno-xl-soft-mul -mxl-barrel-shift -mxl-pattern-compare
-mno-xl-soft-div -mcpu=v7.20.a -O2 -c" "EXTRA_COMPILER_FLAGS=-g"'.
Running libs - 'gmake -s libs "COMPILER=mb-gcc" "ARCHIVER=mb-ar"
"COMPILER_FLAGS=-mno-xl-soft-mul -mxl-barrel-shift -mxl-pattern-compare
-mno-xl-soft-div -mcpu=v7.20.a -O2 -c" "EXTRA_COMPILER_FLAGS=-g"'.
Compiling common
Compiling lldma
Compiling standalone
Compiling mpmc
Compiling emaclite
Compiling uartlite
Compiling intc
Compiling tmrctr
Compiling cpu
Running execs_generate.
Done!
At Local date and time: Fri Jun 19 12:18:46 2009
make -f system.make program started...
mb-gcc -Os /home/users/nicolas/research/SoPC/OS/petalinux-svn/hardware/fs-boot/fs-boot.c
/home/users/nicolas/research/SoPC/OS/petalinux-svn/hardware/fs-boot/srec.c
/home/users/nicolas/research/SoPC/OS/petalinux-svn/hardware/fs-boot/time.c
-o fs-boot/executable.elf \
-Wl,-defsym -Wl,_STACK_SIZE=1K -mno-xl-soft-mul -mxl-barrel-shift
-mxl-pattern-compare -mno-xl-soft-div -mcpu=v7.20.a -g
-I./microblaze_0/include/
-I/home/users/nicolas/research/SoPC/OS/petalinux-svn/hardware/fs-boot/
-L./microblaze_0/lib/ \
-Wall
mb-size fs-boot/executable.elf
text data bss dec hex filename
5258 412 1072 6742 1a56 fs-boot/executable.elf
Done!
At Local date and time: Fri Jun 19 12:33:23 2009
make -f system.make init_bram started...
*********************************************
Initializing BRAM contents of the bitstream
*********************************************
bitinit -p xc4vsx35ff668-10 system.mhs -lp
/home/users/nicolas/research/SoPC/OS/petalinux-svn/hardware/edk_user_repository/
-pe microblaze_0 fs-boot/executable.elf \
-bt implementation/system.bit -o implementation/download.bit
bitinit version Xilinx EDK 11.1 Build EDK_L.29.1
Copyright (c) Xilinx Inc. 2002.
Parsing MHS File system.mhs...
/opt/Xilinx/11.1/EDK /opt/Xilinx/11.1/EDK /opt/Xilinx/11.1/ISE
Overriding IP level properties ...
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 199 - tcl is overriding PARAMETER C_MEM_PART_DATA_WIDTH value
to 16
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 203 - tcl is overriding PARAMETER C_MEM_PART_TRAS value to
45000
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 204 - tcl is overriding PARAMETER C_MEM_PART_TRASMAX value to
120000000
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 205 - tcl is overriding PARAMETER C_MEM_PART_TRC value to 65000
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 206 - tcl is overriding PARAMETER C_MEM_PART_TRCD value to
20000
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 208 - tcl is overriding PARAMETER C_MEM_PART_TWR value to 15000
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 209 - tcl is overriding PARAMETER C_MEM_PART_TRP value to 20000
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 210 - tcl is overriding PARAMETER C_MEM_PART_TMRD value to 2
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 211 - tcl is overriding PARAMETER C_MEM_PART_TRRD value to
15000
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 212 - tcl is overriding PARAMETER C_MEM_PART_TRFC value to
75000
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 213 - tcl is overriding PARAMETER C_MEM_PART_TREFI value to
7800000
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 218 - tcl is overriding PARAMETER C_MEM_PART_CAS_A_FMAX value
to 133
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 219 - tcl is overriding PARAMETER C_MEM_PART_CAS_A value to 2
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 220 - tcl is overriding PARAMETER C_MEM_PART_CAS_B_FMAX value
to 143
INFO:EDK:1560 - IPNAME:mpmc INSTANCE:DDR_SDRAM -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mpmc_v5_00_a/data/mpmc_v2
_1_0.mpd line 221 - tcl is overriding PARAMETER C_MEM_PART_CAS_B value to 2.5
Performing IP level DRCs on properties...
Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Address Map for Processor microblaze_0
(0000000000-0x00001fff) dlmb_cntlr dlmb
(0000000000-0x00001fff) ilmb_cntlr ilmb
(0x44000000-0x47ffffff) DDR_SDRAM microblaze_0_DXCL
(0x44000000-0x47ffffff) DDR_SDRAM microblaze_0_IXCL
(0x80800000-0x80ffffff) FLASH mb_plb
(0x81000000-0x8100ffff) Ethernet_MAC mb_plb
(0x81800000-0x8180ffff) xps_intc_0 mb_plb
(0x83c00000-0x83c0ffff) xps_timer_0 mb_plb
(0x84000000-0x8400ffff) RS232_Uart mb_plb
(0x84400000-0x8440ffff) mdm_0 mb_plb
Computing clock values...
INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:mb_plb -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/plb_v46_v1_04_a/data/plb_
v46_v2_1_0.mpd line 70 - tool is overriding PARAMETER C_PLBV46_NUM_MASTERS
value to 2
INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:mb_plb -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/plb_v46_v1_04_a/data/plb_
v46_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_PLBV46_NUM_SLAVES
value to 6
INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:mb_plb -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/plb_v46_v1_04_a/data/plb_
v46_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_PLBV46_MID_WIDTH
value to 1
INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:mb_plb -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/plb_v46_v1_04_a/data/plb_
v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH value
to 32
INFO:EDK:1560 - IPNAME:lmb_v10 INSTANCE:ilmb -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/data/lmb_
v10_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_LMB_NUM_SLAVES value
to 1
INFO:EDK:1560 - IPNAME:lmb_v10 INSTANCE:dlmb -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/data/lmb_
v10_v2_1_0.mpd line 71 - tool is overriding PARAMETER C_LMB_NUM_SLAVES value
to 1
INFO:EDK:1560 - IPNAME:bram_block INSTANCE:lmb_bram -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/bram_block_v1_00_a/data/b
ram_block_v2_1_0.mpd line 69 - tool is overriding PARAMETER C_MEMSIZE value
to 0x2000
INFO:EDK:1560 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/xps_ethernetlite_v2_01_a/
data/xps_ethernetlite_v2_1_0.mpd line 78 - tool is overriding PARAMETER
C_SPLB_NUM_MASTERS value to 2
INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:FLASH -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_00_a/data/
xps_mch_emc_v2_1_0.mpd line 80 - tool is overriding PARAMETER
C_SPLB_NUM_MASTERS value to 2
INFO:EDK:1560 - IPNAME:xps_uartlite INSTANCE:RS232_Uart -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/xps_uartlite_v1_01_a/data
/xps_uartlite_v2_1_0.mpd line 76 - tool is overriding PARAMETER
C_SPLB_NUM_MASTERS value to 2
INFO:EDK:1560 - IPNAME:xps_timer INSTANCE:xps_timer_0 -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/xps_timer_v1_01_a/data/xp
s_timer_v2_1_0.mpd line 79 - tool is overriding PARAMETER C_SPLB_MID_WIDTH
value to 1
INFO:EDK:1560 - IPNAME:xps_timer INSTANCE:xps_timer_0 -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/xps_timer_v1_01_a/data/xp
s_timer_v2_1_0.mpd line 80 - tool is overriding PARAMETER C_SPLB_NUM_MASTERS
value to 2
INFO:EDK:1560 - IPNAME:mdm INSTANCE:mdm_0 -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_e/data/mdm_v2_1
_0.mpd line 88 - tool is overriding PARAMETER C_SPLB_MID_WIDTH value to 1
INFO:EDK:1560 - IPNAME:mdm INSTANCE:mdm_0 -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_e/data/mdm_v2_1
_0.mpd line 89 - tool is overriding PARAMETER C_SPLB_NUM_MASTERS value to 2
INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -
/opt/Xilinx/11.1/EDK/hw/XilinxProcessorIPLib/pcores/xps_intc_v2_00_a/data/xps
_intc_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_SPLB_NUM_MASTERS
value to 2
Checking platform address map ...
Initializing Memory...
Running Data2Mem with the following command:
data2mem -bm implementation/system_bd -bt implementation/system.bit -bd
fs-boot/executable.elf tag microblaze_0 -o b implementation/download.bit
Memory Initialization completed successfully.
Done!
Generating Block Diagram :
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/blockdiagram/system.svg...
Generating Block Diagram :
/home/users/nicolas/research/SoPC/ML402/microblaze-edk11/blockdiagram/system.svg...
Generated --- system.svg
Generated --- system.svg
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