A. Bose wrote:
I have a modified Xilinx MPMC core that interfaces to SRAM (interface to the XPS remains the same). Each SRAM access is 4x32bit words. So the addressing needs to be 16 byte aligned.Where would I change this memory alignment in the kernel? Or would there be a better place to do this change?
I'm not sure I understand what you've done. Attached an SRAM interface to MPMC - OK.
But the MicroBlaze interface to MPMC is CacheLink (XCL), which has a defined protocol (critical word first, configurable cacheline width).
The kernel won't have anything to do with this, you just need to make sure your memory interface can satisfy the cachelink protocol (sparsely documented in the MicroBlaze user guide).
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