Re: [partial-reconfig] Modules and Bus macro

["Umar Mushtaq" <misfit_05@xxxxxxxxxxx>]

So we're all in unchartered territory... :)

I've now come to the stage in my thesis where the coding is done and I
need to proceed with the partial reconfigurable flow... to stay on the
safe side I'm going with the external lines to control the BMs, even
though using the LUTs appears so much more tempting...

For some reason I get the feeling the infamous "Global_Logic0 or
Global_Logic1" during PAR would be more of an issue if we use LUTs for
0s and 1s... although Xilinx claims that through the "Mode=Reconfig"
constraint you make sure LUTs within modules are used, we can never be
sure since ISE is full of such undocumented quirks...

Lets see what ISE 7.1 brings us...

Sincerely,
Umar
-- 
  Umar Mushtaq
  misfit_05@fastmail.fm

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