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[partial-reconfig] Unable to combine symbols into a singal IOB



Dear All,
 
I'm working in a simple design using EDK Microblaze system and Xilinx Modular Design Flow with ISE 6.2i. The design is composed by two modules. One Fixed (the Microblaze system) and another reconfigurable with a very simple logic.  The reconfigurable modules are synthesized fine but when I try the active phase in the fixed module the following error message is issued:
 
________________________________________________________
 
ERROR:Pack:1107 - Unable to combine the following symbols into a single
 IOB
 component:
 PULL symbol "fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin<0>_PULLDOWN" (Output
 Signal = fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin<0>)
 BUF symbol "sys/iobuf_40/IBUF" (Output Signal = 
sys/fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin_I<0>)
 TBUF symbol "sys/iobuf_40/OBUFT" (Control Signal =
 fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin_T<0>)
 PAD symbol "sys/fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin<0>" (Pad Signal =
 fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin<0>)
 
The component belongs to a closed area group.
 
ERROR:Pack:1107 - Unable to combine the following symbols into a single
 IOB
 component:
 PULL symbol "fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin<1>_PULLDOWN" (Output
 Signal
 = fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin<1>)
 BUF symbol "sys/iobuf_41/IBUF" (Output Signal =
 sys/fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin_I<1>)
 TBUF symbol "sys/iobuf_41/OBUFT" (Control Signal =
 fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin_T<1>)
 PAD symbol "sys/fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin<1>" (Pad Signal =
 fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin<1>)
 
The component belongs to a closed area group.
______________________________________________________________
 
Probally this issue is due the following lines in the ucf file:
 
Net fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin<1> LOC=P20;
Net fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin<1> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin<1> PULLDOWN;
Net fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin<0> LOC=P19;
Net fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin<0> IOSTANDARD = SSTL2_I;
Net fpga_0_DDR_SDRAM_16Mx16_DDR_DQS_pin<0> PULLDOWN;
 
I tried use the following command line:
 
XIL_NGDBUILD_NO_PUSH_IOBUFS=1
 
That is described in Xilinx Support page
 
http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=19845
 
 
But isn't working!!!
 
Somebody can help me about this message error?
 
Thanks in advance,
 
Remy Eskinazi